參數(shù)資料
型號: MBM30LV0128-PFTR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 128 M (16 M X 8) BIT NAND-type
中文描述: 16M X 8 FLASH 2.7V PROM, PDSO48
封裝: PLASTIC, REVERSE, TSOP-48
文件頁數(shù): 23/43頁
文件大?。?/td> 397K
代理商: MBM30LV0128-PFTR
MBM30LV0064
23
D
OUT
I/O0
to I/O7
CLE
ALE
t
CEH
t
CRY
**
t
RB
00h
A
0
to
A
7
Column address
N
A
9
to
A
16
D
N + 1
D
OUT
N
CE
RE
R/B
WE
t
CLS
t
CS
t
CH
t
CLH
t
WC
t
ALS
t
ALH
t
ALH
t
R
t
AR2
t
WB
t
RR
t
RC
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
REA
**:SE = GND input : D
OUT
527
= V
CC
input : D
OUT
511
: V
IH
or V
IL
D
N + 2
A
17
to
A
22
Figure 14 Read Cycle (1) Timing Diagram
Note: The CE signal must stay “Low” after the third address input and during Busy state.
00h
A
17
to
A
22
A
9
to
A
16
A
0
to
A
7
Column address
N ***
D
OUT
N
D
N + 1
D
N + 2
CE
RE
R/B
WE
t
CLS
t
CS
t
CH
t
CLH
t
WC
t
ALS
t
ALH
t
ALH
t
R
t
AR2
t
WB
t
RR
t
RC
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
REA
t
CHZ
t
RHZ
I/O0
to I/O7
***:Read Operation using 00h Command
Read Operation using 01h Command
N : 0 to 255
N : 256 to 511
CLE
ALE
: V
IH
or V
IL
Figure 15 Read Cycle (1) Timing Diagram: Interrupted by CE
Note: The CE signal must stay “Low” after the third address input and during Busy state.
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