Sampling at the falling edge of sampling clock*1 and enabled serial" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MB95F136JBWPF-GE1
寤犲晢锛� Fujitsu Semiconductor America Inc
鏂囦欢闋佹暩(sh霉)锛� 46/64闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32KB FLASH 28SOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� F²MC MB95130MB
鏍稿績铏曠悊鍣細 F²MC-8FX
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫i€氭€э細 LIN锛孲IO锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 19
绋嬪簭瀛樺劜鍣ㄥ閲忥細 32KB锛�32K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.4 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8/10b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 105°C
灏佽/澶栨锛� 28-SOP
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� 865-1075
MB95130MB Series
50
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit
= 1, ECCR register : SCDE bit = 1)
(VCC
= 5.0 V卤 10%, AVSS = VSS = 0.0 V, TA = 40 掳C to + 85 掳C)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to 鈥� (2) Source Clock/Machine Clock鈥� for tMCLK.
Parameter
Sym-
bol
Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operating output pin :
CL
= 80 pF + 1 TTL.
5 tMCLK*3
ns
SCK
鈫撯啋 SOT delay time
tSLOVI
SCK, SOT
95
+95
ns
Valid SIN
鈫� SCK鈫�
tIVSHI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
鈫戔啋 valid SIN hold time
tSHIXI
SCK, SIN
0
ns
SOT
鈫� SCK鈫� delay time
tSOVHI
SCK, SOT
4 tMCLK*3
ns
SCK
SOT
SIN
2.4 V
0.8 V
tSLOVI
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
2.4 V
0.8 V
tSCYC
tSOVHI
tIVSHI
tSHIXI
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