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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MB95F136JBWPF-GE1 |
| 寤犲晢锛� | Fujitsu Semiconductor America Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 18/64闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 32KB FLASH 28SOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | F²MC MB95130MB |
| 鏍稿績铏曠悊鍣細 | F²MC-8FX |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | LIN锛孲IO锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 19 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�32K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8/10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 灏佽/澶栨锛� | 28-SOP |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | 865-1075 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�鐣�(d膩ng)鍓嶇18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�
MB95130MB Series
25
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0078H
(Register bank pointer (RP)
Mirror of direct bank pointer (DP)
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
(Disabled)
0F80H
WRARH0
Wild register address setting register (Upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (Lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (Upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (Lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (Upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (Lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
(Disabled)
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register
ch.0
R/W
00000000B
0F97H
to
0F9BH
(Disabled)
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
to
0FA3H
(Disabled)
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MB95F136JBWPFV | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Microcontrollers |
| MB95F136JS | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Proprietary Microcontrollers |
| MB95F136JSPFV-GE1 | 鍒堕€犲晢:FUJITSU 鍔熻兘鎻忚堪:8BIT MCU 32K FLASH 1K RAM SOP28 |
| MB95F136JW | 鍒堕€犲晢:FUJITSU 鍒堕€犲晢鍏ㄧū:Fujitsu Component Limited. 鍔熻兘鎻忚堪:8-bit Proprietary Microcontrollers |
| MB95F136KSPF-GE1 | 鍒堕€犲晢:FUJITSU 鍔熻兘鎻忚堪: |
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