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53
MB90246A Series
13. DSP Interface for the IIR Filter
The DSP interface for the IIR filter is a unit which covers product addition (
ΣBi × Yj + ΣAm × Xn) by hardware.
This interface allows IIR filter calculation to be performed readily and in a high speed.
The DSP interface for the IIR filter has the following features.
Coefficients A and B, and variables X and Y have 16-bit length, and four banks are supported.
(1 to 4) + (1 to 4) product terms can be selected.
Data can be rounded and clipped in units of 10 or 12 bits.
With two or more concatenated banks used, the results of an operation can be transferred to the subsequent
bank register.
Operation time: ((M + N + 1)
× B + 1)/φ s(M, N = number of product terms, B = number of banks, φ: machine
clock)
(1) Register Configuration
Product addition control status register upper digits (MCSR:H)
Initial value
- XXXXXXX B
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Address
000081H
(MCSR:L)
bit 7
bit 0
.............
—WEY
WENY WENX
N1
N0
M1
M0
—R/W
R/W
Product addition control status register lower digits (MCSR:L)
Initial value
00000000 B
Address
000082H
(MCCR:H)
OVF
CNTD CNTC
CNTB CDRD CDRC CDRB CDRA
R/W
Initial value
XXX0XXX0 B
Address
000080H
(MCSR:H)
RND
CLP
DIV
BF
BNK1
BNK0
TRG
MAE
R/W
R
R/W
W
R/W
Initial value
------ 0 0 B
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Address
000083H
(MCCR:L)
bit 7
bit 0
.............
——
—
RESV
——
—
——
R/W
Initial value
XXXXXXXX B
Address
MDORH : 000088H
D23 D22 D21 D20 D19 D18 D17 D16
D24
D25
D26
D27
D28
D29
D30
D31
bit 7 bit 6 bit 5 bit 4 bit 3bit 2bit 1bit 0
bit 8
bit 9
bit 10
bit 11
bit 12
bit 13
bit 14
bit 15
SS
S
SD34 D33 D32
RR
R
RRRR
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
D10
D11
D12
D13
D14
D15
RR
R
RRRR
R
RR
R
RRRR
R
XXXXXXXX XXXXXXXX B
MDORM : 000086H
MDORL : 000084H
XXXXXXXX XXXXXXXX B
Product addition control register upper digits (MCCR:H)
Product addition control register lower digits (MCCR:L)
Product addition output register (MDORL, M, H)
R/W : Readable and writable
R : Read only
W : Write only
— : Unused
X : Indeterminate
RESV : Reserved bit
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 15
bit 8
............
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 15
bit 8
............