參數(shù)資料
型號： MB90246APFV
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, LQFP-100
文件頁數(shù)： 25/100頁
文件大?。?/td> 1959K
代理商： MB90246APFV
30
MB90246A Series
(3) Register Configuration
(Continued)
(PDR5)
(PDR7)
(PDR9)
(Vacancy)
P17
P16
P15
P14
P13
P12
P11
P10
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
(System reservation area)
(PDR4)
(PDR6)
(PDR8)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P47
P46
P45
P44
P43
P42
P41
P40
P67
P66
P65
P64
P63
P62
P61
P60
P87
P86
P85
P84
P83
P82
—
PA5
PA4
PA3
PA2
PA1
PA0
R/W
—
R/W
P57
P56
P55
P54
P53
P52
P51
P50
—
P76
P75
P74
P73
P72
P71
P70
—
P96
P95
P94
P93
P92
P91
P90
Port 1 data register
(PDR1)
Port 4 data register
(PDR4)
Port 5 data register
(PDR5)
Port 6 data register
(PDR6)
Port 7 data register
(PDR7)
Port 8 data register
(PDR8)
Port 9 data register
(PDR9)
Port A data register
(PDRA)
Address
000001H
Address
000004H
Address
000005H
Address
000006H
Address
000007H
Address
000008H
Address
000009H
Address
00000AH
R/W
—
R/W
bit 15
bit 8
............
bit 15
bit 8
............
bit 15
bit 8
............
bit 15
bit 8
............
P17
P16
P15
P14
P13
P12
P11
P10
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Port 1 direction register
(DDR1)
Address
000011H
(DDR5)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P47
P46
P45
P44
P43
P42
P41
P40
R/W
Port 4 direction register
(DDR4)
Address
000014H
(DDR4)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
P57
P56
P55
P54
P53
P52
P51
P50
Port 5 direction register
(DDR5)
Address
000015H
R/W
(DDR7)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
P67
P66
P65
P64
P63
P62
P61
P60
R/W
Analog input enable register
(ADER)
Address
000016H
bit 15
bit 8
............
bit 15
bit 8
............
bit 7
bit 0
.............
bit 7
bit 0
.............
bit 7
bit 0
.............
bit 7
bit 0
.............
bit 7
bit 0
.............
bit 7
bit 0
.............
(System reservation area)
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