參數(shù)資料
型號(hào): MB86R01PB-GSE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 69/89頁(yè)
文件大?。?/td> 0K
描述: IC SOC GRAPHIC CONTRLR 484BGA
特色產(chǎn)品: Graphics Display Controllers (GDC)
標(biāo)準(zhǔn)包裝: 40
系列:
應(yīng)用: 圖形控制器
核心處理器: ARM9
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
控制器系列:
RAM 容量: 64K x 8
接口: ADC,ATA,CAN,EBI/EMI,I²C,I²S,媒體 LB,PWM,SD 卡,UART/USART,USB
輸入/輸出數(shù): 24
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
其它名稱: 865-1110
65
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
8.5.7.
I2S Signal Timing
Table 8-34
Timing Requirements
Value
Signal
Symbol
Description
Min.
Typ.
Max.
Unit
tscyc
Operating frequency, I2S_SCKx (slave Mode)
0.5*B
MHz
tshw
Pulse duration, I2S_SCKx High (slave Mode)
0.45*T
0.55*T
ns
I2S_SCKx
tslw
Pulse duration, I2S_SCKx Low (slave Mode)
0.45*T
0.55*T
ns
tsfi
Setup time, external I2S_WSx High before I2S_SCKx
Low
(slave mode)
8
ns
I2S_WSx
thfi
Hold time, external I2S_WSx High after I2S_SCKx
Low
(slave Mode)
4
ns
Setup time, I2S_SDIx valid before I2S_SCKx Low
(master mode)
8
ns
tsdi
Setup time, I2S_SDIx valid before I2S_SCKx Low
(slave Mode)
8
ns
Hold time, I2S_SDIx valid after I2S_SCKx Low
(master mode)
4
ns
I2S_SDIx
thdi
Hold time, I2S_SDIx valid after I2S_SCKx Low (slave
mode)
4
ns
B indicates AHB bus clock frequency.
T indicates I2S_SCKx cycle.
Table 8-35
Switching Characteristics
Value
Signal
Symbol
Description
Min.
Typ.
Max.
Unit
tmcyc
Operating frequency, I2S_SCKx (master mode)
0.5*B
MHz
tmhw
Pulse duration, I2S_SCKx high (master mode)
0.45*T
0.55*T
ns
I2S_SCKx
tmlw
Pulse duration, I2S_SCKx low (master mode)
0.45*T
0.55*T
ns
I2S_WSx
tdfs
Delay time, I2S_SCKx High to I2S_WSx transition
(master mode)
-12
12
ns
Delay time, I2S_SCKx High to I2S_SDOx valid except
the first bit of transmit frame. (master mode)
-12
17
ns
tddo
Delay time, I2S_SCKx high to I2S_SDOx valid except
the first bit of transmit frame. (slave mode)
3
32
ns
I2S_SDOx
tdfb1
Delay time, I2S_SCKx high to the first bit of a transmit
frame when FSPH bit of I2Sx_CNTREG register is 1.
(master mode)
-14
17
ns
B indicates AHB bus clock frequency.
T indicates I2S_SCKx cycle.
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