參數(shù)資料
型號: MAX7000S
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 48/62頁
文件大?。?/td> 1173K
代理商: MAX7000S
48
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 34
and
35
show the EPM7256S AC operating conditions.
Table 34. EPM7256S External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
t
PD1
t
PD2
Input to non-registered output
C1 = 35 pF
7.5
10.0
15.0
ns
I/O input to non-registered
output
C1 = 35 pF
7.5
10.0
15.0
ns
t
SU
t
H
t
FSU
Global clock setup time
3.9
7.0
11.0
ns
Global clock hold time
0.0
0.0
0.0
ns
Global clock setup time of fast
input
3.0
3.0
3.0
ns
t
FH
Global clock hold time of fast
input
0.0
0.5
0.0
ns
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
Global clock to output delay
C1 = 35 pF
4.7
5.0
8.0
ns
Global clock high time
3.0
4.0
5.0
ns
Global clock low time
3.0
4.0
5.0
ns
Array clock setup time
0.8
2.0
4.0
ns
Array clock hold time
1.9
3.0
4.0
ns
Array clock to output delay
C1 = 35 pF
7.8
10.0
15.0
ns
Array clock high time
3.0
4.0
6.0
ns
Array clock low time
3.0
4.0
6.0
ns
Minimum pulse width for clear
and preset
(2)
3.0
4.0
6.0
ns
t
ODH
Output data hold time after
clock
C1 = 35 pF
(3)
1.0
1.0
1.0
ns
t
CNT
f
CNT
Minimum global clock period
7.8
10.0
13.0
ns
Maximum internal global clock
frequency
(4)
128.2
100.0
76.9
MHz
t
ACNT
f
ACNT
Minimum array clock period
7.8
10.0
13.0
ns
Maximum internal array clock
frequency
(4)
128.2
100.0
76.9
MHz
f
MAX
Maximum clock frequency
(5)
166.7
125.0
100.0
MHz
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