參數(shù)資料
型號(hào): MAX7000S
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁(yè)數(shù): 37/62頁(yè)
文件大?。?/td> 1173K
代理商: MAX7000S
Altera Corporation
37
MAX 7000 Programmable Logic Device Family Data Sheet
f
ACNT
Maximum internal array clock
frequency
(4)
175.4
142.9
116.3
100.0
MHz
f
MAX
Maximum clock frequency
(5)
250.0
200.0
166.7
125.0
MHz
Table 25. EPM7032S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min
Max
Min
Max
Min
Max
Min
Max
t
IN
t
IO
t
FIN
t
SEXP
t
PEXP
t
LAD
t
LAC
t
IOE
t
OD1
t
OD2
t
OD3
t
ZX1
t
ZX2
t
ZX3
t
XZ
t
SU
t
H
t
FSU
Input pad and buffer delay
0.2
0.2
0.3
0.5
ns
I/O input pad and buffer delay
0.2
0.2
0.3
0.5
ns
Fast input delay
2.2
2.1
2.5
1.0
ns
Shared expander delay
3.1
3.8
4.6
5.0
ns
Parallel expander delay
0.9
1.1
1.4
0.8
ns
Logic array delay
2.6
3.3
4.0
5.0
ns
Logic control array delay
2.5
3.3
4.0
5.0
ns
Internal output enable delay
0.7
0.8
1.0
2.0
ns
Output buffer and pad delay
C1 = 35 pF
0.2
0.3
0.4
1.5
ns
Output buffer and pad delay
C1 = 35 pF
(6)
0.7
0.8
0.9
2.0
ns
Output buffer and pad delay
C1 = 35 pF
5.2
5.3
5.4
5.5
ns
Output buffer enable delay
C1 = 35 pF
4.0
4.0
4.0
5.0
ns
Output buffer enable delay
C1 = 35 pF
(6)
4.5
4.5
4.5
5.5
ns
Output buffer enable delay
C1 = 35 pF
9.0
9.0
9.0
9.0
ns
Output buffer disable delay
C1 = 5 pF
4.0
4.0
4.0
5.0
ns
Register setup time
0.8
1.0
1.3
2.0
ns
Register hold time
1.7
2.0
2.5
3.0
ns
Register setup time of fast
input
1.9
1.8
1.7
3.0
ns
t
FH
Register hold time of fast
input
0.6
0.7
0.8
0.5
ns
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
Register delay
1.2
1.6
1.9
2.0
ns
Combinatorial delay
0.9
1.1
1.4
2.0
ns
Array clock delay
2.7
3.4
4.2
5.0
ns
Register enable time
2.6
3.3
4.0
5.0
ns
Global control delay
1.6
1.4
1.7
1.0
ns
Register preset time
2.0
2.4
3.0
3.0
ns
Table 24. EPM7032S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min
Max
Min Max
Min
Max
Min Max
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