參數(shù)資料
型號： MAX7000S
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 35/62頁
文件大小： 1173K
代理商： MAX7000S
Altera Corporation
35
MAX 7000 Programmable Logic Device Family Data Sheet
Table 23. MAX 7000 & MAX 7000E Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-15
-15T
-20
Min
Max
Min
Max
Min
Max
t
IN
t
IO
t
FIN
t
SEXP
t
PEXP
t
LAD
t
LAC
t
IOE
t
OD1
Input pad and buffer delay
2.0
2.0
3.0
ns
I/O input pad and buffer delay
2.0
2.0
3.0
ns
Fast input delay
(2)
2.0
–
4.0
ns
Shared expander delay
8.0
10.0
9.0
ns
Parallel expander delay
1.0
1.0
2.0
ns
Logic array delay
6.0
6.0
8.0
ns
Logic control array delay
6.0
6.0
8.0
ns
Internal output enable delay
(2)
3.0
–
4.0
ns
Output buffer and pad delay
Slow slew rate = off
V
CCIO
= 5.0 V
Output buffer and pad delay
Slow slew rate = off
V
CCIO
= 3.3 V
Output buffer and pad delay
Slow slew rate = on
V
CCIO
= 5.0 V or 3.3 V
Output buffer enable delay
Slow slew rate = off
V
CCIO
= 5.0 V
Output buffer enable delay
Slow slew rate = off
V
CCIO
= 3.3 V
Output buffer enable delay
Slow slew rate = on
V
CCIO
= 5.0 V or 3.3 V
Output buffer disable delay
C1 = 35 pF
4.0
4.0
5.0
ns
t
OD2
C1 = 35 pF
(7)
5.0
–
6.0
ns
t
OD3
C1 = 35 pF
(2)
8.0
–
9.0
ns
t
ZX1
C1 = 35 pF
6.0
6.0
10.0
ns
t
ZX2
C1 = 35 pF
(7)
7.0
–
11.0
ns
t
ZX3
C1 = 35 pF
(2)
10.0
–
14.0
ns
t
XZ
t
SU
t
H
t
FSU
t
FH
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
C1 = 5 pF
6.0
6.0
10.0
ns
Register setup time
4.0
4.0
4.0
ns
Register hold time
4.0
4.0
5.0
ns
Register setup time of fast input
(2)
2.0
–
4.0
ns
Register hold time of fast input
(2)
2.0
–
3.0
ns
Register delay
1.0
1.0
1.0
ns
Combinatorial delay
1.0
1.0
1.0
ns
Array clock delay
6.0
6.0
8.0
ns
Register enable time
6.0
6.0
8.0
ns
Global control delay
1.0
1.0
3.0
ns
Register preset time
4.0
4.0
4.0
ns
Register clear time
4.0
4.0
4.0
ns
PIA delay
2.0
2.0
3.0
ns
Low-power adder
(8)
13.0
15.0
15.0
ns
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