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| 型號： | MAX7000S |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數(shù)： | 25/62頁 |
| 文件大?。?/td> | 1173K |
| 代理商： | MAX7000S |
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Altera Corporation
25
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
Operating Requirements for Altera Devices Data Sheet.
(2)
inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
V
must rise monotonically.
(5)
The POR time for all 7000S devices does not exceed 300
μ
s. The sufficient V
voltage level for POR is 4.5 V. The
device is fully initialized within the POR time after V
reaches the sufficient POR voltage level.
(6)
3.3-V I/ O operation is not available for 44-pin packages.
(7)
The V
parameter applies only to MAX 7000S devices.
(8)
During in-system programming, the minimum DC input voltage is –0.3 V.
(9)
These values are specified under the MAX 7000 recommended operating conditions in
Table 11 on page 23
.
(10) The parameter is measured with 50
%
of the outputs each sourcing the specified current. The I
OH
parameter refers
to high-level TTL or CMOS output current.
(11) The parameter is measured with 50
%
of the outputs each sinking the specified current. The I
OL
parameter refers to
low-level TTL, PCI, or CMOS output current.
(12) When the JTAG interface is enabled in MAX 7000S devices, the input leakage current on the JTAG pins is typically
–60
μ
A.
(13) Capacitance is measured at 25
°
C and is sample-tested only. The
OE1
pin has a maximum capacitance of 20 pF.
Figure11
shows the typical output drive characteristics of MAX 7000
devices.
Figure 11. Output Drive Characteristics of 5.0-V MAX 7000 Devices
Timing Model
MAX 7000 device timing can be analyzed with the Altera software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in
Figure12
. MAX 7000
devices have fixed internal delays that enable the designer to determine
the worst-case timing of any design. The Altera software provides timing
simulation, point-to-point delay prediction, and detailed timing analysis
for a device-wide performance evaluation.
V
O
Output Voltage (V)
1
2
3
4
5
30
60
90
150
120
V
= 3.3 V
Room Temperature
I
OL
I
OH
3.3
V
O
Output Voltage (V)
1
2
3
4
5
30
60
90
150
120
V
= 5.0 V
Room Temperature
I
OL
I
OH
I
O
Typical
Output
Current (mA)
I
O
Typical
Output
Current (mA)
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