參數(shù)資料
型號(hào)： MAX7000S
廠商： Altera Corporation
英文描述： Programmable Logic Device Family
中文描述： 可編程邏輯器件系列
文件頁數(shù)： 36/62頁
文件大?。?/td> 1173K
代理商： MAX7000S
36
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
Table 11
. See
Figure 13
for more
information on switching waveforms.
(2)
This parameter applies to MAX 7000E devices only.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The
t
parameter
must be added to this minimum width if the clear or reset signal incorporates the
t
LAD
parameter into the signal
path.
(4)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(5)
These parameters are measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.
(6)
The
f
values represent the highest frequency for pipelined data.
(7)
Operating conditions: V
= 3.3 V
±
10
%
for commercial and industrial use.
(8)
The
t
parameter must be added to the
t
LAD
, t
LAC
, t
IC
, t
EN
,
t
SEXP
,
t
ACL
, and
t
CPPW
parameters for macrocells
running in the low-power mode.
Tables 24
and
25
show the EPM7032S AC operating conditions.
Table 24. EPM7032S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min Max
Min
Max
Min Max
Min
Max
t
PD1
t
PD2
Input to non-registered output
C1 = 35 pF
5.0
6.0
7.5
10.0
ns
I/O input to non-registered
output
C1 = 35 pF
5.0
6.0
7.5
10.0
ns
t
SU
t
H
t
FSU
Global clock setup time
2.9
4.0
5.0
7.0
ns
Global clock hold time
0.0
0.0
0.0
0.0
ns
Global clock setup time of fast
input
2.5
2.5
2.5
3.0
ns
t
FH
Global clock hold time of fast
input
0.0
0.0
0.0
0.5
ns
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
Global clock to output delay
C1 = 35 pF
3.2
3.5
4.3
5.0
ns
Global clock high time
2.0
2.5
3.0
4.0
ns
Global clock low time
2.0
2.5
3.0
4.0
ns
Array clock setup time
0.7
0.9
1.1
2.0
ns
Array clock hold time
1.8
2.1
2.7
3.0
ns
Array clock to output delay
C1 = 35 pF
5.4
6.6
8.2
10.0
ns
Array clock high time
2.5
2.5
3.0
4.0
ns
Array clock low time
2.5
2.5
3.0
4.0
ns
Minimum pulse width for clear
and preset
(2)
2.5
2.5
3.0
4.0
ns
t
ODH
Output data hold time after
clock
C1 = 35 pF
(3)
1.0
1.0
1.0
1.0
ns
t
CNT
f
CNT
Minimum global clock period
5.7
7.0
8.6
10.0
ns
Maximum internal global clock
frequency
(4)
175.4
142.9
116.3
100.0
MHz
t
ACNT
Minimum array clock period
5.7
7.0
8.6
10.0
ns
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