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Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
MAX5816
Maxim Integrated Products 17
I2C Write Operation (Multibyte Operation)
The MAX5816 supports a multibyte transfer protocol for
some commands. In multibyte mode, once a command
is issued (with multibyte bit = 1), that command is con-
tinuously executed based on two byte data blocks for
the duration I2C operation. Essentially, bytes 1 to 4 are
processed normally, but for every two bytes of data pro-
vided after byte 4, the originally requested command is
executed again with the latest byte pair provided as input
data. Multibyte protocol is enforced until a STOP condi-
tion (or repeated START) is encountered, this provides a
higher speed transfer mode that is useful in servo DAC
applications.
Combined Format I2C Readback
Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in
Figure 6. The first byte contains
the address of the MAX5816 with R/W = 0 to indicate a
write. The second byte contains the register that is to be
read back. There is a Repeated START condition, fol-
lowed by the device address with R/W = 1 to indicate a
read and an acknowledge clock. The master has control
of the SCL line but the MAX5816 takes over the SDA line.
The final two bytes in the frame contain the register data
readback followed by a STOP condition. If additional
bytes beyond those required to readback the requested
data are provided, the MAX5816 will continue to read-
back ones.
Readback of individual CODE registers is supported for
all the user CODE commands. For these commands,
which support a DAC address, the requested channel
CODE register content will be returned; if all DACs are
selected, CODE A content will be returned.
Readback of individual DAC registers is supported for
all user LOAD and CODE_LOAD commands. For these
commands, which support a DAC address, the request-
ed DAC register content will be returned. If all DACs are
selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command. The power status of each DAC
is reported in locations B[3:0], with a 1 indicating the
DAC is powered down and a zero indicating the DAC is
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status device ID and revision
information in the format is shown in
Table 2.Interface Verification I2C
Readback Operations
While the MAX5816 supports standard I2C readback of
selected registers, it is also capable of functioning in an
interface verification mode. This mode is accessed any
time a readback operation follows an executed write
mode command. In this mode, the last executed three-
byte command is read back in its entirety. This behavior
allows verification of the interface.
Sample command sequences are shown in
Figure 7. The
first command transfer is given in write mode with R/W =
0 and must be run to completion to qualify for interface
verification readback. There is now a STOP/START pair
or Repeated START condition required, followed by the
readback transfer with R/W = 1 to indicate a read and an
acknowledge clock from the MAX5816. The master still
has control of the SCL line but the MAX5816 takes over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5816 will continue
to read back ones.
Table 2. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
READBACK DATA LOW BYTE
R7 R6 R5 R4 R3 R2 R1 R0 B15 B14 B13 B12 B11 B10 B9 B8
B7
B6
B5
B4
B3
B2
B1
B0
0
X
0
A2 A1 A0
CODEn[11:4]
CODEn[3:0]
0
X
0
1
A2 A1 A0
DACn[11:4]
DACn[3:0]
0
X
0
1
0
A2 A1 A0
DACn[11:4]
DACn[3:0]
0
X
0
1
A2 A1 A0
DACn[11:4]
DACn[3:0]
0
X
1
0
X
0
0 PWD PWC PWB PWA
0
X
1
0
1
X
1
0
1
0
1
0
REV_ID
[2:0]
(010)
REF
MODE
[1:0]
0
X
1
0
X
0
X
1
X