![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/MAX5816ATB-T_datasheet_101827/MAX5816ATB-T_18.png)
Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
MAX5816
Maxim Integrated Products 18
Figure 6. I2C Multibyte Register Write Sequence (Multibyte Protocol)
Figure 7. Standard I2C Register Read Sequence
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
SCL
A
W
N N N N
A
N
D D D D D D D
A
D
START
SDA
N
0 0 0 1 1 A1 A0
1
0
STOP
D D D D D D D
A
D
D D D D D D D
A
D
D D D D D D D
A
D
ACK. GENERATED BY I2C MASTER
ACK. GENERATED BY MAX5816
REG N UPDATED
WRITE ADDRESS
BYTE #1: DEVICE ADDRESS
WRITE REGISTER NO.
BYTE #2: FIRST REG# = N
WRITE DATA
BYTE #3: REG(N)[15:8] DATA
WRITE DATA
BYTE #4: REG(N)[7:0] DATA
ADDITIONAL DATA BYTE PAIRS
(2 BYTE BLOCKS)
WRITE DATA
BYTE #X-1: REG(N)[15:8] DATA
WRITE DATA
BYTE #X: REG(N)[7:0] DATA
A
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
REPEATED
START
READ ADDRESS
BYTE #3: I2C SLAVE
ADDRESS
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
ACK. GENERATED BY MAX5816
ACK. GENERATED BY I2C MASTER
A
START
STOP
SCL
SDA
00 01 1A1A0W AA
0 0N
0 00 11 A1 A0 RA D DDD DD DD
DDDDDDDD ~A
A
NN NNN
SCL
A
W
20 19 18 17
A
16
15 14 13 12 11 10 9A
8
START
SDA
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
21
0 0 0 1 1 A1 A0
22
23
STOP
7 6 5 4 3 2 1A
0
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
20 19 18 17
A
16
15 14 13 12 11 10 9A
8
21
22
23
7 6 5 4 3 2 1A
0
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
COMMAND1
EXECUTED
COMMANDn
EXECUTED
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
ACK. GENERATED BY MAX5816
A