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Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
MAX5816
Maxim Integrated Products 20
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involving
other devices do not impact the MAX5816 readback mode.
Toggling between readback modes is based on the length
of the preceding write mode transfer. Combined format I2C
readback operation is resumed if a write command greater
than two bytes but less than four bytes is supplied. For
commands written using multiple register write sequences,
only the last command executed is read back. For each
command written, the readback sequence can only be
completed one time; partial and/or multiple attempts to
readback executed in succession will not yield usable data.
I2C Compatibility
The MAX5816 is fully compatible with existing I2C sys-
tems. SCL and SDA are high-impedance inputs; SDA has
an open drain which pulls the data line low to transmit
data or ACK pulses. Figure 9 shows a typical I2C appli- cation.
I2C User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5816.
Table 3 provides detailed information about the Command
Registers.
Figure 9. Typical I2C Application Circuit
C
ADDR
SCL
SDA
SCL
SDA
ADDR
+5V
SCL
SDA
MAX5816