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| 型號： | MAX5816ATB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL 4CH 10TDFN |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 4.5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.95W |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-TDFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
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Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
MAX5816
Maxim Integrated Products 14
Detailed Description
The MAX5816 is a 4-channel, low-power, 12-bit buff-
ered voltage-output DAC. The 2.7V to 5.5V wide supply
voltage range and low-power consumption accommo-
dates most low-power and low-voltage applications. The
device presents a 100kI load to the external reference.
The internal output buffers allow rail-to-rail operation.
An internal voltage reference is available with software
selectable options of 2.048V, 2.5V, or 4.096V. The device
features a fast 400kHz I2C-compatible interface. The
MAX5816 includes a serial-in/parallel-out shift register,
internal CODE and DAC registers, a power-on-reset
(POR) circuit to initialize the DAC outputs to code zero,
and control logic.
DAC Outputs (OUT_)
The MAX5816 includes internal buffers on all DAC out-
puts. The internal output buffers provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive up to 2kI in parallel with 500pF.
Under no-load conditions, the output buffers drive from
GND to VDD, subject to offset and gain errors. With a 2kω
load to GND, the output buffers drive from GND to within
200mV of VDD. With a 2kω load to VDD, the output buffers
drive to within 200mV of GND and VDD.
The DAC ideal output voltage is defined by:
OUT
REF
N
D
VV
2
=
×
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the reg-
ister contents. SW_CLEAR and SW_RESET commands
(both clear and reset modes) reset the contents of all
CODE and DAC registers to their zero-scale defaults.
Internal Reference
The MAX5816 includes an internal precision voltage ref-
erence that is software selectable to be 2.048V, 2.500V,
or 4.096V. When an internal reference is selected, that
voltage is available on the REF pin for other external cir-
cuitry (see Figure 9) and can drive a 25kI load.
External Reference
The external reference input has a typical input imped-
ance of 100kI and accepts an input voltage from +1.24V
to VDD. Connect an external voltage supply between REF
and GND to apply an external reference. The MAX5816
powers up and resets to external reference mode. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
I2C Serial Interface
The MAX5816 features an I2C-/SMBusK-compatible,
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL enable
communication between the MAX5816 and the master
at clock rates up to 400kHz. Figure 1 shows the 2-wire
interface timing diagram. The master generates SCL
and initiates data transfer on the bus. The master device
writes data to the MAX5816 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5816 is 8
bits long and is followed by an acknowledge clock pulse.
A master reading data from the MAX5816 must transmit
the proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5816
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or Repeated START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and
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