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參數(shù)資料
| 型號： | MAX5816ATB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL 4CH 10TDFN |
| 產(chǎn)品培訓(xùn)模塊： | Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 4.5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.95W |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-TDFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
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Ultra-Small, Quad-Channel, 12-Bit Buffered Output DAC
with Internal Reference and I2C Interface
MAX5816
Maxim Integrated Products 15
an open-drain output. A pullup resistor, typically 4.7kI is
required on SDA. SCL operates only as an input. A pullup
resistor, typically 4.7kI, is required on SCL if there are
multiple masters on the bus, or if the single master has
an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5816
from high voltage spikes on the bus lines and mini-
mize crosstalk and undershoot of the bus signals. The
MAX5816 can accommodate bus voltages higher than
VDD up to a limit of 5.5V; bus voltages lower than VDD
are not recommended and may result in significantly
increased interface currents.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5816. The master terminates transmission
and frees the bus, by issuing a STOP condition. The bus
remains active if a Repeated START condition is gener-
ated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
The MAX5816 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Transmissions ending in an early STOP condition will not
impact the internal device settings. If the STOP occurs
during a readback byte, the transmission is terminated
and a later read mode request will begin transfer of the
requested register data from the beginning (this applies
to combined format I2C read mode transfers only,
interface verification mode transfers will be corrupted).
See Figure 2.
I2C Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the R/W bit. See
Figure 4. The five most significant bits are 00011 with the
2 LSBs determined by ADDR as shown in Table 1. Setting
the R/W bit to 1 configures the MAX5816 for read mode.
Setting the R/W bit to 0 configures the MAX5816 for write
mode. The slave address is the first byte of information
sent to the MAX5816 after the START condition.
The MAX5816 has the ability to detect an unconnected
state on the ADDR input for additional address flexibility;
if leaving the ADDR input unconnected, be certain to
minimize all loading on the pin (i.e. provide a landing for
the pin, but do not allow any board traces).
Figure 2. I2C START, Repeated START, and STOP Conditions
Table 1. I2C Slave Address LSBs for
TDFN Package
ADDR
A1
A0
VDD
0
N.C.
1
0
GND
1
SCL
SDA
SSrP
VALID START, REPEATED START, AND STOP PULSES
PS
P
SP
P
S
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
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