SPI/I2C UART with 128-Word FIFOs Low-Power Operation To reduce the power consump" />
參數(shù)資料
型號: MAX3107ETG+T
廠商: Maxim Integrated Products
文件頁數(shù): 43/52頁
文件大?。?/td> 0K
描述: IC UART SPI/I2C 128 FIFO 24TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
特點: 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TQFN-EP(3.5x3.5)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX3107ETG+TDKR
SPI/I2C UART with 128-Word FIFOs
Low-Power Operation
To reduce the power consumption during normal opera-
tion, the following techniques can be adopted:
Do not use the internal PLL. This saves the most power
of the options listed here. Disable and bypass the PLL.
With the PLL enabled, the current to the VA supply is
in the range of a few mA (depending on clock and
multiplication factor), while it drops to below 1mA if
disabled.
Keep the internal clock rates as low as possible.
Use low voltage on the VA supply.
Use an external 1.8V supply. This saves the power
dissipated in the internal 1.8V linear regulator for the
1.8V logic supply. Connect the external 1.8V supply to
V18 and disable the internal regulator by connecting
LDOEN to DGND.
Interrupts and Polling
The host controller can manage and control the MAX3107
through polling and/or through interrupts. In polled
mode, the IRQ physical interrupt output is not used and
the host controller polls the ISR register at frequent inter-
vals to establish the state of the MAX3107.
Alternatively, the MAX3107’s physical IRQ interrupt
can be used to interrupt the host controller at specified
events, making polling unnecessary. The IRQ output is
an open-drain output that requires a pullup resistor to VL.
Logic-Level Translation
The MAX3107 can be directly connected to transceivers
and controllers that have different supply voltages. The
VL input defines the logic voltage levels of the control-
ler interface while the VEXT voltage defines the logic of
the transceiver interface. This ensures flexibility when
selecting a controller and transceiver. Figure 24 is an
example of a setup when the controller, transceiver, and
the MAX3107 are powered by three different supplies.
Figure 23. Startup and Initialization Flowchart
POWER-UP/
RST INPUT PULLED HIGH/
RST BIT SET LOW
IS IRQ HIGH?
OR
RevID READ
SUCCESSFULLY
Y
N
CONFIGURE
CLOCKING
CONFIGURE
MODES
CONFIGURE
FIFO CONTROL
CONFIGURE
FLOW CONTROL
CONFIGURE
GPIOs
START
COMMUNICATION
ENABLE
INTERRUPTS
48
Maxim Integrated
MAX3107
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