SPI/I2C UART with 128-Word FIFOs Bit 7: RTS The RTS bit gives direct control of " />
參數(shù)資料
型號： MAX3107ETG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 27/52頁
文件大?。?/td> 0K
描述： IC UART SPI/I2C 128 FIFO 24TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
特點： 內(nèi)部振蕩器
通道數(shù)： 4，QUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.35 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TQFN-EP（3.5x3.5）
包裝： 標準包裝
其它名稱： MAX3107ETG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bit 7: RTS
The RTS bit gives direct control of the RTS/CLKOUT output logic. If the RTS bit is set high, then RTS/CLKOUT is set to
logic-high. The RTS bit only works if the CLKSource[7]:CLKtoRTS is not set high.
Bit 6: TxBreak
Set TxBreak to 1 to generate a line break whereby the TX output is held low until TxBreak is set to 0.
Bit 5: ForceParity
ForceParity enables forced parity, as used in 9-bit multidrop communication. Set both LCR[3] and ForceParity to use
forced parity. The parity bit is forced high by the transmitter if LCR[4] low. The parity bit is forced low if LCR[4] is high.
Bit 4: EvenParity
Set EvenParity high to enable even parity. If EvenParity is set low odd parity generation/checking is used.
Bit 3: ParityEn
The ParityEn bit enables the use of a parity bit on the TX and RX interfaces. When ParityEn is low, then parity usage
is disabled. When ParityEn is set to 1, the transmitter generates the parity bit as defined in LCR[4] and the receiver
checks the received parity bit.
Bit 2: StopBits
This defines the number of STOP bits and depends on the length of the word programmed in LCR[1:0] (Table 1). When
StopBits is high and the word length is 5, the transmitter generates a word with a STOP bit length equal to 1.5. Under
these conditions, the receiver recognizes a STOP bit length greater than a 1-bit duration.
Bits 1 and 0: Length[1:0]
The Length[1:0] bits configure the length of the words that the transmitter generates and the receiver checks for at the
asynchronous TX and RX interfaces (Table 2).
LCR—Line Control Register
Table 1. StopBits Truth Table
Table 2. Length[1:0] Truth Table
ADDRESS:
0x0B
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
RTS
TxBreak
ForceParity
EvenParity
ParityEn
StopBits
Length1
Length0
RESET
0
1
0
1
LCR[2]
WORD LENGTH
STOP BIT LENGTH
0
5, 6, 7, 8
1
5
1–1.5
1
6, 7, 8
2
Length1
Length0
WORD LENGTH
0
5
0
1
6
1
0
7
1
8
Maxim Integrated
33
MAX3107
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MAX3108AEWA+ 制造商:Maxim Integrated Products 功能描述:LOW SHUTDOWN CURRENT SPI/I?C UART WITH 128-WORD FIFOS IN WLP - Rail/Tube
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