SPI/I2C UART with 128-Word FIFOs Bit 7: CLKtoRTS Set the CLKtoRTS bit to 1 to ro" />
參數(shù)資料
型號: MAX3107ETG+T
廠商: Maxim Integrated Products
文件頁數(shù): 38/52頁
文件大小: 0K
描述: IC UART SPI/I2C 128 FIFO 24TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
特點: 內(nèi)部振蕩器
通道數(shù): 4,QUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.35 V ~ 3.6 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應商設備封裝: 24-TQFN-EP(3.5x3.5)
包裝: 標準包裝
其它名稱: MAX3107ETG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bit 7: CLKtoRTS
Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock
frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
Bits 6 and 5: No Function
Bit 4: ClockEn
Set the ClockEn bit high to enable an external clocking (crystal or clock generator at XIN). Set the ClockEn bit to 0 to
disable clocking.
Bit 3: PLLBypass
Set the PLLBypass bit high to enable bypassing the internal PLL and predivider.
Bit 2: PLLEn
Set the PLLEn bit high to enable the internal PLL. If PLLEn is set low, the internal PLL is disabled.
Bit 1: CrystalEn
Set the CrystalEn bit high to enable the crystal oscillator. When using an external clock source at XIN, CrystalEn must
be set low.
Bit 0: No Function
Always keep Bit 0 at logic 0.
Bit 7–0: Bit[7:0]
The RevID register indicates the revision number of the MAX3107 silicon, starting with 0xA1. This can be used during
software development.
CLKSource—Clock Source Register
RevID—Revision Identification Register
ADDRESS:
0x1E
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
CLKtoRTS
ClockEn
PLLBypass
PLLEn
CrystalEn
RESET
0
1
0
ADDRESS:
0x1F
MODE:
R
BIT
7
6
5
4
3
2
1
0
NAME
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESET
1
0
1
0
1
Maxim Integrated
43
MAX3107
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