SPI/I2C UART with 128-Word FIFOs Bits 7 and 4: No Function Bit 6: SleepIntEn Set" />
參數(shù)資料
型號： MAX3107ETG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 24/52頁
文件大?。?/td> 0K
描述： IC UART SPI/I2C 128 FIFO 24TQFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
特點： 內(nèi)部振蕩器
通道數(shù)： 4，QUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.35 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TQFN-EP（3.5x3.5）
包裝： 標準包裝
其它名稱： MAX3107ETG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bits 7 and 4: No Function
Bit 6: SleepIntEn
Set the SleepIntEn bit high to route the SleepInt status bit to the ISR[2]: STSInt. If set low, the STSIntEn masks the ISR[2]
bit from SleepInt.
Bit 5: ClkRdyIntEn
Set the ClkRdyIntEn bit high to route the ClockReady status bit to the ISR[2]: STSInt bit. If set low, the ClkRdyIntEn
masks the ISR[2] bit from the ClockReady status.
Bits 3–0: GPI[3:0]IntEn
The GPI[3:0]IntEn bits that are set high route the associated STSInt[3:0]: GPI[3:0]Int bits to the ISR[2] interrupt. GPI[3:0]
IntEn bits that are set low, mask the ISR[2] interrupt from the associated GPI[3:0]Int bit.
Bits 7 and 4: No Function
Bit 6: SleepInt
The SleepInt bit is set when the MAX3107 enters sleep mode. The SleepInt bit is cleared when the MAX3107 exits sleep
mode. This status bit is cleared when the clock is disabled and cannot be cleared upon reading. The SleepInt bit can
generate an ISR[2]: STSInt interrupt, if enabled through STSIntEn[6].
Bit 5: ClockReady
The ClockReady bit is set high when the clock, the divider, and the PLL have settled, and the MAX3107 is ready for
data communication. The ClockReady bit only works with the crystal oscillator. It does not work with external clocking
through XIN.
The ClockReady status bit is cleared when the clock is disabled and is not cleared upon read. This bit can generate
an ISR[2]: STSInt interrupt, if enabled through STSIntEn[5].
Bits 3–0: GPI[3:0]Int
The GPI[3:0]Int interrupts are set high when a change of logic state occurs on the associated GPIO_ input. GPI[3:0]Int
is cleared upon reading. These interrupts can be selectively routed to the ISR[2] interrupt bit through the STSIntEn[3:0].
STSIntEn—STS Interrupt Enable Register
STSInt—Status Interrupt Register
ADDRESS:
0x07
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
—
SleepIntEn
ClkRdyIntEn
—
GPI3IntEn
GPI2IntEn
GPI1IntEn
GPI0IntEn
RESET
0
ADDRESS:
0x08
MODE:
R/COR
BIT
7
6
5
4
3
2
1
0
NAME
—
SleepInt
ClockReady
—
GPI3Int
GPI2Int
GPI1Int
GPI0Int
RESET
0
30
Maxim Integrated
MAX3107
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