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| 型號： | MAX19527EVKIT+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/30頁 |
| 文件大小： | 0K |
| 描述： | EVAL KIT MAX19527 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
15
Internal Reference Mode
In a typical application, the internal absolute gain
accuracy is sufficient and the internal reference is
used to establish the full-scale range of the ADC. An
external 0.1FF bypass capacitor from REFIO to GND is
recommended. An external bypass capacitor placed
across REFH and REFL is required to achieve optimal
near-carrier noise performance, and a value of 0.1FF is
recommended to achieve the performance specified in
the Electrical Characteristics table.
When using sleep mode for power management, the
wake-up time is determined by the reference-bypass
capacitor values. The wake-up from sleep-mode
characteristic appears as ADC gain vs. time where the
ADC full-scale voltage is to first order a 2-pole response.
The first pole is established by the RC time constant
on pin REFIO. The second pole is established by the
RC time constant on pins REFH and REFL. When the
recommended capacitor values are used, the wake-up
from sleep time is 10ms. When nap mode is used for
power management, the reference remains powered on
and the wake-up time from nap mode is not affected by
the reference bypass capacitance values.
External Reference Mode
In applications where control over the full-scale range
of the ADC is desired, an external voltage of 1.25V
can be applied to REFIO. For optimal performance, the
recommended adjustment range is limited to +5/-15%.
The REFIO-to-ADC gain-transfer function is:
VFS = 1.5 x [VREFIO/1.25]
As in the case of internal reference mode, apply a
0.1FF capacitor across pins REFH and REFL to achieve
optimal near-carrier noise performance and provide
noise filtering of the external reference source.
Clock Input
The input clock interface provides for flexibility in the
requirements of the clock driver. The device accepts a
fully differential clock or single-ended logic-level clock.
The device is specified for an input sampling frequency
range of 25MHz to 50MHz. By default, the internal PLL
is configured to accept input clock frequencies from
39MHz to 50MHz. The PLL is programmed through the
PLL Sampling Rate register (00h, Table 2). Table 3 details
the complete range of PLL sampling frequency settings.
For differential clock operation, connect a differential
clock to the CLKIN+ and CLKIN- inputs. The input
common mode is established internally to allow for
AC-coupling. The self-biased input common-mode
voltage defaults to 1.2V. The differential clock signal
can also be DC-coupled if the externally established
common-mode voltage is constrained to the specified
clock input common-mode range of 1.0V to 1.4V. A
differential input termination of 100I can be switched
in by programming the CLKIN Control register (04h[4],
Table 17).
For single-ended operation, connect CLKIN- to GND
and drive the CLKIN+ input with a logic-level signal.
When the CLKIN- input is grounded (or pulled below the
threshold of the clock-mode detection comparator), the
differential-to-single-ended conversion stage is disabled
and the logic-level inverter path is activated. The input
common-mode self-bias is disconnected from CLKIN+,
and provides a weak pullup bias to AVDD for CLKIN-
during single-ended clock operation (Figure 4).
System Timing Requirements
Figure 5 shows the relationship between the analog
inputs, input clock, frame-alignment output, serial-clock
output, and serial-data outputs. The differential analog
input (IN_+, IN_-) is sampled on the rising edge of the
applied clock signal (CLKIN+, CLKIN-) and the result-
ing data appears at the digital outputs 8.5 clock cycles
later. Figure 6 provides a detailed, two-conversion timing
diagram of the relationship between inputs and outputs.
Clock Output (CLKOUT+, CLKOUT-)
The ADC provides a differential clock output that con-
sists of CLKOUT+ and CLKOUT-. As shown in Figure
6, the serial output data is clocked out of the device on
both edges of the clock output. The frequency of the
output clock is six times (6x) the frequency of the input
clock. The Output Data Format and Test Pattern register
(01h) allows the phase of the clock output to be adjusted
relative to the output data frame (Table 5, Figure 10).
Frame-Alignment Output (FRAME+, FRAME-)
The ADC provides a differential frame-alignment signal
that consists of FRAME+ and FRAME-. As shown in
Figure 6, the rising edge of the frame-alignment signal
corresponds to the first bit (D0) of the 12-bit serial-data
stream. The frequency of the frame-alignment signal is
identical to the frequency of the input clock; however, the
duty cycle varies depending on the input clock frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19527EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19527 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19527EXE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19527EXE+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19528EVKIT+ | 制造商:Maxim Integrated Products 功能描述:ANALOG TO DIGITAL CONVERTER - Boxed Product (Development Kits) |
| MAX19528EXE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 12BIT 8CH 64MSPS 144CTBGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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