- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17005 > MAX19527EVKIT+ (Maxim Integrated Products)EVAL KIT MAX19527 PDF資料下載
參數(shù)資料
| 型號： | MAX19527EVKIT+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT MAX19527 |
| 標準包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
18
The LVDS output drivers also feature optional internal
termination that can be enabled and adjusted by the
LVDS Output Driver Management register (03h, Table
14). By default, the internal output driver termination is
disabled. See Table 16 for all possible configurations.
Output Driver Level Tests
The LVDS outputs (data, clock, and frame) can be
configured to static logic-level test states through the
LVDS Output Driver Level register (02h, Table 9). The
complete list of settings for the static logic-level test
states can be found in Tables 10, 11, and 12.
Data Output Test Patterns
The LVDS data outputs can be configured to
output several different, recognizable test patterns. Test
patterns are enabled and selected using the Output
Data Format and Test Pattern register (01h, Table 5). A
complete list of test pattern options is listed in Table
7, and custom test pattern details can be found in the
Custom Test Pattern Registers (07h, 08h, 09h) section
(including Tables 21, 22, and 23).
Power Management
The SHDN input is used to toggle between two power-
management states. Power state 0 corresponds to SHDN
= 0, while power state 1 corresponds to SHDN = 1. The
PLL Sampling Rate and Power Management register
(00h) and the Channel Power Management registers
(05h and 06h) fully define each power-management
state. By default, SHDN = 1 shuts down the device and
SHDN = 0 returns the ADCs to full-power operation. Use
of the SHDN input is not required for power management.
For either state of SHDN, complete power-manage-
ment flexibility is provided, including individual ADC
channel power-management control, as well as the
option of which reduced power-mode to utilize in each
power state. The available reduced-power modes are
called sleep mode and nap mode. The device cannot
enter either of these states unless no ADC channels are
active in the current power state (Table 4).
In nap mode, the reference, duty-cycle equalizer, and
clock-multiplier PLL circuits remain active for rapid
wake-up time. In nap mode, the externally applied clock
signal must remain active for the duty-cycle equalizer
and PLL to remain locked. Typical wake-up time from
nap mode is 2Fs.
In sleep mode, all circuits are turned off except for the
bandgap voltage-generation circuit. All registers retain
previously programmed values during sleep mode.
Typical wake-up time from sleep mode is 10ms, which
is dominated by the RC time constants on REFIO and
REFH/REFL.
Power On and Reset
The user-programmable register default settings and
other factory-programmed settings are stored in a non-
volatile memory. Upon device power-up, these values are
loaded into the control registers. The operation occurs
after the application of a valid supply voltage to AVDD
and OVDD, and the presence of an input clock signal.
The user-programmed register values are retained as
long as the AVDD and OVDD voltages are applied.
A reset condition overwrites all user-programmed
registers with the default factory values. The reset
condition occurs on power-up and can be initiated while
powered with a software write command (write 5Ah)
through the serial-port interface to the Special Function
register (10h). The reset time is proportional to the ADC
clock period and requires 415Fs at 50Msps.
3-Wire Serial Peripheral Interface (SPI)
The ADC operates as a slave device that sends
and receives data through a 3-wire SPI interface. A
master device must initiate all data transfers to and from
the device. The device uses an active-low SPI chip-
select input (CS) to enable communication with timing
controlled through the externally generated SPl clock
input (SCLK). All data is sent and received through the
bidirectional SPI data line (SDIO). The device has 10
user-programmable control registers and one special-
function register, which are accessed and programmed
through this interface.
SPI Communication Format
Figure 8 shows an ADC SPI communication cycle.
All SPI communication cycles are made up of two
bytes of data on SDIO and require 16 clock cycles on
SCLK to be completed. To initiate an SPI read or write
communication cycle, CS must first transition from a
logic-high to a logic-low state. While CS remains low,
serial data is clocked in from SDIO on rising edges of
SCLK and clocked out (for a read) on the falling edges
of SCLK. When CS is high, the device does not respond
to SCLK transitions, and no data is read from or written
to SDIO. CS must transition back to logic-high after each
read/write cycle is completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SRR0805-681K | INDUCTOR PWR 680UH 10% SHLD SMD |
| ADR431BRZ-REEL7 | IC VREF SERIES PREC 2.5V 8-SOIC |
| VI-JWH-EY | CONVERTER MOD DC/DC 52V 50W |
| MAX11131EVKIT# | EVAL KIT MAX11131 |
| MAX11635EVSYS# | KIT EVAL SYSTEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19527EVKIT+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19527 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19527EXE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19527EXE+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19528EVKIT+ | 制造商:Maxim Integrated Products 功能描述:ANALOG TO DIGITAL CONVERTER - Boxed Product (Development Kits) |
| MAX19528EXE+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 12BIT 8CH 64MSPS 144CTBGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。