參數(shù)資料
型號(hào): MAX19527EVKIT+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 18/30頁(yè)
文件大小: 0K
描述: EVAL KIT MAX19527
標(biāo)準(zhǔn)包裝: 1
系列: *
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
25
CPM: SHDN0 is 1111-1111, which causes power
state 0 to enable all eight channels (by default). The
CPM: SHDN1 register (06h) is used to enable or disable
each channel for power state 1 (SHDN = 1). The default
state of CPM: SHDN1 is 0000-0000, which causes power
state 1 to disable all eight channels (by default). Both
power states are independently configurable for any
combination of enabled and disabled channels (Tables
19 and 20).
Custom Test Pattern Registers (07h, 08h, 09h)
The Custom Test Pattern (1, 2, and 3) registers are used to
create a user-programmed test pattern sequence (TEST_
DATA = 1, TEST_PATTERN[2:0] = 010, see Tables 5 and
7). The data for the custom test pattern sequence is divided
among the three Custom Test Pattern registers (Tables 21,
22, and 23). The custom test pattern comprises a series
of two, 12-bit sequences (BITS_CUSTOM1[11:0] first,
followed by BITS_CUSTOM2[11:0]) that repeat continu-
ously.
Table 17. Input Common Mode and CLKIN Control (04h)
Table 18. Input Common-Mode Voltage Configuration
Table 19. Channel Power Management: SHDN0 (05h)
Table 20. Channel Power Management: SHDN1 (06h)
Table 21. Custom Test Pattern 1 (07h)
Table 22. Custom Test Pattern 2 (08h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CLKIN_TERM
CMI_ADJ[2:0]
CMI_SELF
CMI_ADJ[2:0]
INPUT COMMON-MODE VOLTAGE (mV)
0
1020
0
1
1040
0
1
0
1060
0
1
1080
1
0
1100 (default)
1
0
1
1120
1
0
1140
1
1160
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CH8_SHDN0
CH7_SHDN0
CH6_SHDN0
CH5_SHDN0
CH4_SHDN0
CH3_SHDN0
CH2_SHDN0
CH1_SHDN0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CH8_SHDN1
CH7_SHDN1
CH6_SHDN1
CH5_SHDN1
CH4_SHDN1
CH3_SHDN1
CH2_SHDN1
CH1_SHDN1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BITS_CUSTOM1[7:0]
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BITS_CUSTOM2[7:0]
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