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參數(shù)資料
| 型號： | MAX19527EVKIT+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT MAX19527 |
| 標準包裝： | 1 |
| 系列： | * |
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Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
20
The PLL[2:0] bits (00h[6:4]) are used to program the
clock multiplier for the internal PLL in order to set the
input sampling frequency range. The default setting
is PLL[2:0] = 001, which allows for 39MHz to 50MHz
operation. See Table 3 for the full range of PLL settings
and the corresponding sampling frequencies.
The NAP_SHDN1 (00h[1]) and NAP_SHDN0 (00h[0]) bits
are used to set the state of the ADC when all channels
are turned off for the SHDN = 1 and SHDN = 0 power-
management states, respectively. When they are set to
logic 0, the device enters sleep mode if no channels are
enabled in that power state. When they are set to logic
1, the device instead enters nap mode if no channels
are enabled for that power state. If even one channel
is active in the current power state, the device cannot
enter nap or sleep mode (Table 4). The default states
are NAP_SHDN1 = 0 and NAP_SHDN0 = 1, meaning
that if all channels are disabled in the corresponding
power state, SHDN = 1 corresponds to sleep mode and
SHDN = 0 corresponds to nap mode.
Output Data Format and Test Pattern Register (01h)
The Output Data Format and Test Pattern register (01h,
Table 5) has several functions. The first is used to adjust
the LVDS output bit order and data format. The second is
used to set the CLKOUT phase with respect to the output
frame. Finally, this register is used to enable and select
test pattern outputs.
Table 1. Summary of User-Programmable Control Registers
Table 3. PLL Frequency Control Settings (00h[6:4])
Table 2. PLL Sampling Rate and Power Management (00h)
X = Don’t care.
ADDRESS
READ/WRITE
POR STATE
FUNCTION
00h
R/W
0001-0001
PLL sampling rate and power management
01h
R/W
0000-0000
Output data format and test patterns
02h
R/W
0000-0000
LVDS output driver level
03h
R/W
0000-0000
LVDS output driver management
04h
R/W
0000-1000
Input common mode and CLKIN control
05h
R/W
1111-1111
Channel power management: SHDN0
06h
R/W
0000-0000
Channel power management: SHDN1
07h
R/W
1010-1010
Custom test patterns 1
08h
R/W
0101-0101
Custom test patterns 2
09h
R/W
0101-1010
Custom test patterns 3
0Ah to 0Fh
—
Reserved
Reserved registers (do not use)
10h
R/W
—
Special function
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
—
PLL[2:0]
—
NAP_SHDN1
NAP_SHDN0
CLOCK MULTIPLIER SETTING
MINIMUM SAMPLING
FREQUENCY (MHz)
MAXIMUM SAMPLING
FREQUENCY (MHz)
PLL[2]
PLL[1]
PLL[0]
0
Not used
0
1
39
50
0
1
0
28.5
39
0
1
25
28.5
1
X
Not used
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19527EVKIT+ | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 MAX19527 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX19527EXE+ | 功能描述:模數(shù)轉換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19527EXE+T | 功能描述:模數(shù)轉換器 - ADC 12Bit 8Ch 50Msps 1.8V ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX19528EVKIT+ | 制造商:Maxim Integrated Products 功能描述:ANALOG TO DIGITAL CONVERTER - Boxed Product (Development Kits) |
| MAX19528EXE+ | 功能描述:模數(shù)轉換器 - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 12BIT 8CH 64MSPS 144CTBGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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