
16
Maxim Integrated
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
MAX13325/MAX13326
Applications Information
Serial Interface
Writing to the MAX13325/MAX13326 using I2C requires
that first the master sends a START (S) condition fol-
lowed by the device’s I2C address. After the address,
the master sends the register address of the register
that is to be programmed. The master then ends com-
munication by issuing a STOP (P) condition to relinquish
control of the bus, or a Repeated START (Sr) condition to
communicate to another I2C slave (see Figure 1).
Bit Transfer
Each SCL rising edge transfers one data bit. The data
on SDA must remain stable during the high portion of the
SCL clock pulse (see Figure 2). Changes in SDA while
SCL is high are read as control signals (see the START
and STOP Conditions section). When the serial interface
is inactive, SDA and SCL idle high.
Figure 1. I2C Timing
Figure 2. Bit Transfer
Table 17. Overvoltage Diagnostic
tLOW
tF
SDA
SCL
tHD:STA
S
tSU:STA
tHD:DAT
tHIGH
tLOW
tSU:DAT
tF
tHD:STA
tSP
P
tSU:STO
S
Sr
tBUF
tR
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE OF
DATA ALLOWED
FAULT CONDITION
STATUS REPORT
UNMASK
RECOVERY
Overvoltage
Shutdown
FLAG is asserted low.
In GMASK register, set
MDUMP bit to 1.
See Table 8.
VDD voltage falls below overvoltage
threshold. Cleared on reading the
GFAULT register. Note: 500ms
autoretry in stand-alone mode.
FLAG bit set. See Table 7.
DUMP bit is set in the GFAULT
register. See Table 4.
Left and right channels switch
off and output goes to a
high-impedance state.
Cannot be masked.
Left channel is enabled by setting
the RETRYL bit to 1. Right channel
is enabled by setting the RETRYR
bit to 1. See Table 3.