
13
Maxim Integrated
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
MAX13325/MAX13326
Right-Channel Mask Register
MSVDDR: Set MSVDDR to 1 to enable the short to VDD detection on the right channel.
MSGNDR: Set MSGNDR to 1 to enable the short to GND detection on the right channel.
MLIMITR: Set MLIMITR to 1 to enable overcurrent detection on the right channel.
MOFFSETR: Set MOFFSETR to 1 to enable excessive-offset detection on the right channel.
MOPENR: Set MOPENR to 1 to enable open-load detection on the right channel.
Table 10. Right-Channel Mask Register
Table 11. Output Short to VDD/Battery Diagnostic
I2C and Stand-Alone Diagnostics
When the DIAG bit and the appropriate mask bits are set
to 1, the MAX13325/MAX13326 enter diagnostic mode.
In this mode, the MAX13325/MAX13326 detect short
to GND, short to battery, overcurrent condition, over-
temperature condition, excessive offset, and report the
diagnosis using the I2C serial interface, FLAG bit, and
the FLAG output.
For stand-alone mode, there exists a 500ms stand-alone
fault retry function (for autoretry) until the fault goes
away. The FLAG output is pulsed to indicate a fault.
Output Short to VDD
When in diagnostic mode, the MAX13325/MAX13326
detect if any of the differential outputs is shorted to VDD
or battery. Upon detection of the short to VDD or battery,
the faulted channel is switched off and its output goes
into a high-impedance state. The fault is reported using
the I2C interface and the FLAG output. See Table 11.
FUNCTION
ADDRESS
CODE
(HEX)
REGISTER DATA
POR
STATE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Right-Channel
Mask Register
0x08
MSVDDR
MSGNDR
MLIMITR
0
MOFFSETR
MOPENR
x
0x00
FAULT CONDITION
STATUS REPORT
UNMASK
RECOVERY
Left-Channel Output
Short to VDD
FLAG is asserted low.
In LMASK register, set
MSVDDL bit to 1.
See Table 9.
Cleared on reading the LFAULT
register. See Table 5.
Note: 500ms autoretry in stand-
alone mode.
FLAG bit set. See Table 7.
SVDDL bit is set in the LFAULT
register. See Table 5.
Left channel switches off and output
goes to high-impedance state.
Cannot be masked.
Output is enabled by setting the
RETRYL bit to 1 in the Common
Byte register. See Table 3.
Right-Channel
Output Short to VDD
FLAG is asserted low.
In RMASK register, set
MSVDDR bit to 1. See
Table 10.
Cleared on reading the RFAULT
register. See Table 6.
Note: 500ms autoretry in stand-
alone mode.
FLAG bit set. See Table 7.
SVDDR bit is set in the RFAULT
register. See Table 6.
Right channel switches off and
output goes to high-impedance
state.
Cannot be masked.
Output is enabled by setting the
RETRYR bit to 1 in the Command
Byte register. See Table 3.