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參數(shù)資料
型號: MAX13326GUI/V+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/21頁
文件大小: 0K
描述: IC AUD LINE DVR DL AUTO 28TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 線路驅(qū)動器,發(fā)射器
應(yīng)用: 車載音頻
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.173",4.40mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
11
Maxim Integrated
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
MAX13325/MAX13326
General Faults
TWARN: The TWARN bit is set to ‘1’ when the temperature warning threshold is reached.
TSHDN: The TSHDN is set to ‘1’ when the temperature shutdown threshold is reached.
DUMP: The DUMP bit is set to ‘1’ when the VDD voltage exceeds the overvoltage threshold.
Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.
Left-Channel Faults
SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.
SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.
LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.
Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.
When any bit of the LFAULT register is high, the FLAG output is low.
Right-Channel Faults
SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.
SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.
LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.
Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.
When any bit of the RFAULT register is high, the FLAG output is pulled low.
Table 4. General Fault Register Format
Table 5. Left-Channel Fault Register Format
Table 6. Right-Channel Fault Register Format
FUNCTION
ADDRESS
CODE (HEX)
REGISTER DATA
POR STATE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
General Fault
Register
0x02
x
TWARN
TSHDN
DUMP
x
0x00
FUNCTION
ADDRESS
CODE
(HEX)
REGISTER DATA
POR STATE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Left-Channel
Fault Register
0x03
SVDDL
SGNDL
LIMITL
x
OFFSETL
OPENL
x
0x00
FUNCTION
ADDRESS
CODE
(HEX)
REGISTER DATA
POR STATE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Right-Channel
Fault Register
0x04
SVDDR
SGNDR
LIMITR
x
OFFSETR
OPENR
x
0x00
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