參數(shù)資料
型號(hào)： MAX109EHF-D
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： ADC
英文描述： 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs
中文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA256
封裝： 27 X 27 MM, 1.27 MM PITCH, SBGA-256
文件頁(yè)數(shù)： 6/29頁(yè)
文件大?。?/td> 451K
代理商： MAX109EHF-D
M
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
6
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = 5V, V
CC
O = 3.3V, V
EE
= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f
CLK
= 2.2Gsps, analog input
amplitude at -1dBFS differential, clock input amplitude 400mV
P-P
differential, digital output pins differential R
L
= 100
. Typical values
are at T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
SFDR
300
SFDR
1000
SFDR
1600
SFDR
2500
SFDR
500
SFDR
1600
SINAD
300
SINAD
1000
f
IN
= 1000MHz, f
CLK
= 2.2Gsps (Note 8)
SINAD
1600
f
IN
= 1600MHz, f
CLK
= 2.2Gsps (Note 8)
SINAD
2500
f
IN
= 2500MHz, f
CLK
= 2.2Gsps
SINAD
500
f
IN
= 500MHz, f
CLK
= 2.5Gsps
SINAD
1600
f
IN
= 1600MHz, f
CLK
= 2.5Gsps
IM3
f
IN1
= 1590MHz, f
IN2
= 1610MHz at -7dBFS
CONDITIONS
MIN
TYP
61.7
51.1
50.3
45.0
53.7
44.6
44.1
43.1
42.1
40.1
43.1
40.5
-60
10
-14
MAX
UNITS
f
IN
= 300MHz, f
CLK
= 2.2Gsps
f
IN
= 1000MHz, f
CLK
= 2.2Gsps (Note 8)
f
IN
= 1600MHz, f
CLK
= 2.2Gsps (Note 8)
f
IN
= 2500MHz, f
CLK
= 2.2Gsps
f
IN
= 500MHz, f
CLK
= 2.5Gsps
f
IN
= 1600MHz, f
CLK
= 2.5Gsps
f
IN
= 300MHz, f
CLK
= 2.2Gsps
44.4
43.7
Spurious Free Dynamic Range
dBc
40.4
37.9
Signal-to-Noise-Plus-Distortion
Ratio
dB
Third-Order Intermodulation
Metastability Probability
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse-Width Low
Clock Pulse-Width High
Aperture Delay
Aperture Jitter
Reset Input Data Setup Time
Reset Input Data Hold Time
dBc
f
CLK(MAX)
t
PWL
t
PWH
t
AD
t
AJ
t
SU
t
HD
t
PD1
2.2
180
180
Gsps
ps
ps
ps
ps
ps
ps
t
CLK
= t
PWL
+ t
PWH
(Note 8)
t
CLK
= t
PWL
+ t
PWH
(Note 8)
200
0.2
(Note 8)
(Note 8)
DCO = f
CLK
/ 4, CLK fall to DCO rise time
DCO = f
CLK
/ 8, DDR mode, CLK fall to
DCO rise time
300
250
1.6
t
PD1DDR
1.6
CLK-to-DCO Propagation Delay
t
PD1QDR
DCO = f
CLK
/ 16, QDR mode, CLK fall to
DCO rise time
1.6
ns
t
PD2
DCO = f
CLK
/ 4, DCO rise to data transition
(Note 8)
-520
+520
t
PD2DDR
DCO = f
CLK
/ 8, DDR mode, DCO rise to
data transition (Note 8)
-520 +
2t
CLK
2t
CLK
520 +
2t
CLK
DCO-to-Data Propagation Delay
t
PD2QDR
DCO = f
CLK
/ 16, QDR mode, DCO rise to
data transition (Note 8)
-520 +
2t
CLK
2t
CLK
520 +
2t
CLK
ps
DCO Duty Cycle
Clock mode independent
45 to
55
%
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