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參數(shù)資料
| 型號： | MAX109EHF-D |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, BGA256 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, SBGA-256 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MAX109EHF-D |
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M
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
20
______________________________________________________________________________________
CLKN
CLKP
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLKP
t
PD1DDR
t
PD2DDR
DCON
DCOP
PORTA DATA
PORTB DATA
NOTE:
THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
PORTC DATA
PORTD DATA
SAMPLE HERE
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 4
N
N + 6
N + 3
N + 5
N + 8
N + 7
N + 1
N + 2
N + 6
N + 7
N + 8
N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
Figure 7. Timing Diagram for DDR Mode, fCLK/ 8 Mode
CLKN
CLKP
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLKP
t
PD1QDR
t
PD2QDR
DCON
DCOP
PORTA DATA
PORTB DATA
NOTE:
THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
PORTC DATA
PORTD DATA
SAMPLE HERE
FROM DLL IN FPGA
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 4
N
N + 6
N + 3
N + 5
N + 8
N + 7
N + 1
N + 2
N + 6
N + 7
N + 8
N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
Figure 8. Timing Diagram for QDR Mode, fCLK/ 16 Mode
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