參數(shù)資料
型號(hào)： M6MGB166S4BWG
廠商： Mitsubishi Electric Corporation
英文描述： CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-CSP
中文描述： 3.3的CMOS只快閃記憶體
文件頁(yè)數(shù)： 28/30頁(yè)
文件大?。?/td> 253K
代理商： M6MGB166S4BWG
Nov. 1999 , Rev.3.2
MITSUBISHI LSIs
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
M6MGB/T166S4BWG
28
Write cycle (S-LB#,S-UB# control mode)
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S-CE1# low, S-CE2 high overlaps S-LB# and/or S-UB# low and W low.
Note 5: When the falling edge of S-WE# is simultaneously or prior to the falling edge of S-LB# and/or S-UB# or the falling edge of
S-CE1# or rising edge of S-CE2, the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
t
h
(D)
t
su
(D)
DQ
0~15
t
su
(LB) or
t
su
(UB)
t
rec
(W)
t
su
(A)
t
CW
A
0~16
,
S-A
17
S-WE#
DATA IN
STABLE
(Note3)
(Note3)
(Note4)
(Note5)
(Note3)
(Note3)
S-CE1#
S-LB#,
S-UB#
(Note3)
(Note3)
S-CE2
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