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參數(shù)資料
| 型號(hào)： | M6MGB166S4BWG |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-CSP |
| 中文描述： | 3.3的CMOS只快閃記憶體 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 253K |
| 代理商： | M6MGB166S4BWG |
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Nov. 1999 , Rev.3.2
MITSUBISHI LSIs
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
M6MGB/T166S4BWG
12
Erase and Program Performance
Block Erase Time
Main Block Write Time (Page Mode)
Page Write Time
Parameter
ms
sec
ms
Unit
Typ
4
1.0
40
Max
80
1.8
600
Min
Program Suspend Latency / Erase Suspend Time
Program Suspend Latency
Erase Suspend Time
Parameter
Unit
Typ
Max
15
15
Min
m
s
m
s
Please see page 20.
Vcc Power Up / Down Timing
Symbol
Unit
Typ
2
Max
Min
t
VCS
Please see page 13.
Parameter
F-RP# =V
IH
set-up time from Vccmin
m
s
Write Mode
(F-CE# control)
AC ELECTRICAL CHARACTERISTICS
(Ta = -40 ~ 85
°
C, F-Vcc = 2.7V ~ 3.6V)
Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at F-Vcc=3.3V, Ta=25
°
C
Symbol
Parameter
Write cycle time
Address set-up time
Data hold time
F-OE# hold from F-CE# high
Latency between Read and Write FFH or 71H
Data set-up time
Address hold time
t
AVAV
t
AVWH
t
EHDX
t
EHGL
-
t
DVWH
t
EHAX
t
WC
t
AS
t
DH
t
OEH
t
RE
t
DS
t
AH
Limits
90ns
Typ
90
50
0
50
0
10
30
Max
Min
Unit
ns
ns
ns
ns
ns
ns
ns
F-CE# pulse width
F-CE# pulse width high
F-OE# hold to F-CE# Low
Write enable hold time
Write enable set-up time
F-RP# high recovery to write enable low
Block Lockhold from valid SRD
Duration of auto-program operation
Duration of auto-block erase operation
F-CE# high to F-RY/BY# low
Block Lock set-up to write enable high
t
ELEH
t
EHEL
t
GHEL
t
EHWH
t
WLEL
t
PHWL
t
QVPH
t
EHRH1
t
EHRH2
t
EHRL
t
PHHEH
t
EHRL
t
PS
t
CEP
t
CEPH
t
GHEL
t
WH
t
WS
t
BLS
t
BLH
t
DAP
t
DAE
150
4
40
90
80
600
60
30
90
0
0
0
90
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
F-Vcc=2.7-3.6V
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2
m
sec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin
during power up/down.
By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down.
During power up, F-RP# must be held VIL for min.2
m
s from the time F-Vcc reaches F-Vccmin.
During power down, F-RP# must be held VIL until Vcc reaches GND.
F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation.
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