參數(shù)資料
型號： M66291GP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 93/128頁
文件大?。?/td> 928K
代理商： M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 65 of 122
(6) INTM (DMA Interrupt Mode) Bit (b9)
This bit sets the timing of setting “1” to the EPB_RDY bit.
<When set to OUT buffer (EPi_DIR bit = “0”)>
When this bit is set to “0”, the EPB_RDY bit is set to “1” after reading all buffer data including the
received short packet (including the zero-length packet) <buffer ready interrupt occurs>.
In case of reading the buffer, the buffer state as well as the bits below are retained. This enables the
reading of the received data length using the buffer ready interrupt.
IVAL bit of the Dn_FIFO Control Register (“1” retained)
DMA_DTLN bits of the Dn_FIFO Control Register
It is necessary to write “1” to the BCLR bit and to clean the buffer in order to receive the next data.
Thus clears the IVAL bit to “0”, and the EPB_RDY bits also are cleared if the RDYM bit is set to “0”. If
the RDYM bit is set to “1”, the EPB_RDY bits are cleared to “0” by writing “0” to the EPB_RDY bit.
When this bit is set to “1”, the EPB_RDY bit is set to “1” under the same conditions as the endpoint not
specified by the DMA_EP bits (buffer ready interrupt occurs).
<When set to IN buffer (EPi_DIR bit = “1”)>
When this bit is set to “0”, the EPB_RDY bit cannot be set to “1”.
When this bit is set to “1”, the EPB_RDY bit is set to “1” under the same conditions as the endpoint not
specified by the DMA_EP bits (buffer ready interrupt occurs).
Note:
Do not use with DMAEN = “0” when this bit is set to “0”.
(7) DMAEN (DMA Enable) Bit (b8)
This bit sets the enable/disable of the output of the DREQ signal for DMA transfer.
When this bit is set to “1”, the DMA transfer is set to enable mode, making the DREQ signal ready for
assertion.
When this bit is written to “0”, the DMA transfer is disabled, allowing no output of DREQ signal.
Note:
Do not use with INTM = “0” when this bit is set to “0”.
(8) BSWP (Byte Swap Mode) Bit (b7)
This bit sets the endian of the Dn_FIFO Data Register.
When this bit is set to “0”, the Dn_FIFO Data Register gets such as little endian.
When this bit is set to “1”, the Dn_FIFO Data Register gets such as big endian.
b15~b8
b7~b0
Little Endian
odd number address
even number address
Big Endian
even number address
odd number address
Note:
Don’t set this bit to “1” when the mode is set to 8-bit (set by the Octl bit or *HWR/*BYTE pin).
相關(guān)PDF資料
PDF描述
M68HC08AZ0 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQFP100
M69030 GRAPHICS PROCESSOR, PBGA278
MA4T85633 C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR
MA4T85600 Si, RF POWER TRANSISTOR
MA4T85635 C BAND, Si, NPN, RF SMALL SIGNAL TRANSISTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66291GP#201 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP
M66291GP#RB0S 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
M66291GPRB0S 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48
M66291HP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller)
M66291HP#200D 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*