參數(shù)資料
型號： M66291GP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝： 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù)： 46/128頁
文件大小： 928K
代理商： M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 22 of 122
2.8 Interrupt Enable Register 0
Interrupt Enable Register 0 (INT_ENABLE0)
<Address : H’10>
b15
14
13
12
11
10
9876
54321
b0
VBSE
RSME
SOFE
DVSE
CTRE BEMPE INTNE
INTRE
URST
SADR
SCFG
SUSP
WDST
RDST
CMPL
SERR
0000
000000
0
00000
0000
000000
0
00000
----
------
<H/W reset : H'0000>
<S/W reset : H'0000>
<USB bus reset : ->
b
Bit name
Function
R
W
15
VBSE
Vbus Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when VBUS bit is set to “1”)
14
RSME
Resume Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when RESM bit is set to "1")
13
SOFE
SOF Detect Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when SOFR bit is set to "1")
12
DVSE
Device State Transition Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when DVST bit is set to "1")
11
CTRE
Control Transfer Transition Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt is occurs when CTRT bit is set to "1")
10
BEMPE
Buffer Empty/Size Over Error Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt is occurs when BEMP bit is set to "1")
9
INTNE
Buffer Not Ready Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when INTN bit is set to "1")
8
INTRE
Buffer Ready Interrupt Enable
0 :
Disable interrupt
1 :
Enable interrupt
(Interrupt occurs when INTR bit is set to "1")
7
URST
USB Reset Detect
0 :
Disable DVST bit set
1 :
Enable DVST bit set
6
SADR
SET_ADDRESS Execute
0 :
Disable DVST bit set
1 :
Enable DVST bit set
5SCFG
SET_CONFIGURATION Execute
0 :
Disable DVST bit set
1 :
Enable DVST bit set
4SUSP
Suspend Detect
0 :
Disable DVST bit set
1 :
Enable DVST bit set
3WDST
Control Write Transfer Status Stage
0 :
Disable CTRT bit set
1 :
Enable CTRT bit set
2
RDST
Control Read Transfer Status Stage
0 :
Disable CTRT bit set
1 :
Enable CTRT bit set
1CMPL
Control Transfer Complete
0 :
Disable CTRT bit set
1 :
Enable CTRT bit set
0
SERR
Control Transfer Sequence Error
0 :
Disable CTRT bit set
1 :
Enable CTRT bit set
This register sets enable of interrupt and enable/disable of setting DVST and CTRT bits to “1”.
Also refer to “3.1 Interrupt Function”.
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相關代理商/技術參數(shù)
參數(shù)描述
M66291GP#201 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP
M66291GP#RB0S 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
M66291GPRB0S 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48
M66291HP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller)
M66291HP#200D 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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