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參數(shù)資料
| 型號： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 121/128頁 |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 90 of 122
3.4 Control Transfer Overview
The control transfer is composed of three stages as follows:
(1) Setup stage
(2) Data stage (some control transfers don't include)
(3) Status stage
The M66291 automatically controls the stages of the control transfers by the hardware and is capable of
generating interrupt against the aforesaid stage transition.
The control transfers are executed by the endpoint 0.
The examples of control write transfer, control read transfer, control write no data transfer, control transfer
error and continuous setup operations are shown in Figure 3.7 to Figure 3.12.
(1) Setup stage
The transition to the setup stage occurs when the setup token is received.
The request data received at the setup stage (8 bytes) is automatically stored to four registers (Request, Value,
Index and Length) before the ACK response is executed.
For SET_ADDRESS request and SET_CONFIGURATION request, the M66291 can respond automatically to
the host. As for the other requests, execute data analysis (decoding) and processing by the software after the
setup stage complete interrupt has occurred.
When the setup token is received, the VALID bit is set to “1”, the EP0_PID and CCPL bits are changed as
shown below, then these bits are protected until the VALID bit is cleared:
EP0_PID bits
“00”
: NAK response (response at data stage)
CCPL bit
“0”
: NAK response (response at status stage)
(2) Data stage
The transition to the data stage occurs when the IN token/OUT token is received after the setup stage. In case
of the request with no data stage, the transition to the status stage executes by receiving the OUT token after
the setup stage.
Control write transfer (OUT transaction)
With the buffer set to receive ready state (buffer empty), the EP0_PID bits are set to “01” to make ACK
response to the host after receiving the data.
When the buffer is ready for data reading, the buffer ready interrupt occurs to enable reading of the
receive data by the EP0_FIFO Data Register.
Control read transfer (IN transaction)
With the buffer set to transmit ready state (buffer contains transmit data), the data is transmitted to
the host by setting the EP0_PID bits to “01”.
When the buffer is ready to accept new transmit data, the buffer ready interrupt occurs.
(3) Status stage
The transition to the status stage occurs when IN token and OUT token are received after the data stage,
causing the control write/read transfer status transition interrupt to occur. In this case, setting the EP0_PID
bits to “01” and the CCPL bit to “1” enables to notify the normal completion to the host.
In the case of the request with no data stage, this interrupt works as the setup stage complete interrupt.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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