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參數(shù)資料
| 型號： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 58/128頁 |
| 文件大?。?/td> | 928K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 33 of 122
(12) CTSQ (Control Transfer Stage) Bits (b2~b0)
These bits indicate the present stage in the control transfer. Refer to Figure 2.7.
000 : Idle or Setup Stage
001 : Control Read Transfer Data Stage
010 : Control Read Transfer Status Stage
011 : Control Write Transfer Data Stage
100 : Control Write Transfer Status Stage
101 : Control Write No Data Transfer Status Stage
110 : Control Transfer Sequence Error (refer to below)
111 : Reserved
The control transfer sequence error is described below. When this error occurs, the EP0_PID bits are set to
“1x” (stall state).
<At control read transfer>
OUT token is received when data is never transferred against the IN token of the data stage.
IN token is received at status stage.
Data packet other than the zero-length packet is received at status stage.
<At control write transfer>
IN token is received when ACK response is never made against the OUT token of the data
stage.
OUT token is received in status stage.
<At control write no data transfer>
OUT token is received in status stage.
<Others>
Data exceeding in size set by the EP0 Packet Size Register is received (the EPB_EMP_OVR
bit of the Interrupt Status Register 3 is set to “1”).
In case the amount of received data exceeds the wLength value in the request at the data stage of the
control write transfer, it is not recognized as the control transfer sequence error.
[CTSQ bits ="1xx "]
Control transfer
sequence error
(Note )
ACK
receive
ACK transmit
Note : When the SERR bit is set to "1" and the control transfer sequence error causes the CTRT interrupt to
occur, the CTSQ bit values (1xx) are retained until "0" is written to the CTRT bit (interrupt is cleared).
Further, even after the completion of the next set up stage, the CTRT interrupt due to the completion
of the set up stage is not occurred until "0" is written to the CTRT bit.
When the SERR bit is set to "0", if setup token is received, the CTSQ bits changes to "000".
Error detection
: CTRTinterrupt has occurred
(1) Setup stage completion
(2) Control read transfer
status stage transition
(3) Control write transfer
status stage transition
(4) Control transfer completion
(5) Control transfer
sequence error
[CTSQ bits ="000"]
Setup stage
[CTSQ bits ="011"]
Control write
transfer
data stage
[CTSQ bits ="101"]
Control write
transfer no data
status stage
ACK
transmit
[CTSQ bits ="010"]
Control read
transfer
status stage
[CTSQ bits ="100"]
Control write
transfer
status stage
OUT token
receive
IN token receive
[CTSQ bits ="000"]
Idle stage
ACK
receive
[CTSQ bits ="001"]
Control read
transfer
data stage
Setup token receive
(1)
Setup token receive
(1)
(3)
(2)
(5)
(4)
Figure 2.7 Control Transfer Transition
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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