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參數(shù)資料
| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 78/112頁 |
| 文件大?。?/td> | 1862K |
| 代理商： | M38B79MFH-XXXXFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
65
f(XIN)/128
f(XCIN)
1/4
1/2
1/1
f(XCIN)
Counter sampling
clock selection bit
INT2 interrupt input
Noise filter
8-bit binary up
counter
Interrupt interval
determination register
address 003016
Data bus
Divider
One-sided/both-sided
edge detection
selection bit
Noise filter sampling
clock selection bit
Counter overflow
interrupt request
or remote control
interrupt request
Divider
1/1
1/2
f(XIN)/32
Internal system
clock selection bit
Internal system
clock selection bit
INTERRUPT INTERVAL DETERMINATION FUNCTION
The 38B7 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising edge (falling edge) of an input signal pulse on the P72/
INT2 pin to the rising edge (falling edge) of the signal pulse that is
input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interrupt interval determination operat-
ing).
3. Select the sampling clock of 8-bit binary up counter by setting
bit 1 of the interrupt interval determination control register.
4. When the signal of polarity which is set on the INT2 pin (rising
or falling edge) is input, the 8-bit binary up counter starts count-
ing up of the selected counter sampling clock.
5. When the signal of polarity selected above is input again, the
value of the 8-bit binary up counter is transferred to the inter-
rupt interval determination register (address 003016), and the
remote control interrupt request occurs. Immediately after that,
the 8-bit binary up counter continues to count up again from
“0016”.
6. When count value reaches “FF16”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16” to the in-
terrupt interval determination register to generate the counter
overflow interrupt request.
Fig. 68 Interrupt interval determination circuit block diagram
Noise Filter
The P72/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “0016”.
2. The P72/INT2 input signal is sampled in synchronization with
the selected clock. When sampling the same level signal in a
series of three sampling, the signal is recognized as the inter-
rupt signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control regis-
ter to “1”, the interrupt request can occur at both rising and falling
edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
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