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參數(shù)資料
| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 73/112頁 |
| 文件大?。?/td> | 1862K |
| 代理商： | M38B79MFH-XXXXFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
60
b7 b6 b5
b4 b3
b2 b1 b0
AD/DA control register
(ADCON: address 003216)
Analoginput pin selection bits
b3b2b1b0
0 0 0 0 : PA0/AN0
0 0 0 1 : PA1/AN1
0 0 1 0 : PA2/AN2
0 0 1 1 : PA3/AN3
0 1 0 0 : PA4/AN4
0 1 0 1 : PA5/AN5
0 1 1 0 : PA6/AN6
0 1 1 1 : PA7/AN7
1 0 0 0 : P90/SIN3/AN8
1 0 0 1 : P91/SOUT3/AN9
1 0 1 0 : P92/SCLK3/AN10
1 0 1 1 : P93/SRDY3/AN11
1 1 0 0 : P94/RTP1/AN12
1 1 0 1 : P95/RTP0/AN13
1 1 1 0 : P96/PWM0/AN14
1 1 1 1 : P97/BUZ02/AN15
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
DA output enable bit
0 : DA output disabled
1 : DA output enabled
Not used (returns “0” when read)
AD conversion register (high-order)
(ADH: address 003416)
b7
b0
b7 b6 b5
b4
b3 b2
AD conversion register (low-order)
(ADL: address 003316)
b7
b0
b1 b0
b9 b8
Note: When reading the low-order 6 bits at address 003316,
“0” is read out.
Data bus
AVSS
A-D interrupt request
b7b0
4
AD/DA control register
C
h
a
n
e
l
s
e
le
c
to
r
Comparator
A-D control circuit
A-D conversion register (H)
(Address 003416)
(Address 003316)
Resistor ladder
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
P90/SIN3/AN8
P91/SOUT3/AN9
P92/SCLK3/AN10
P93/SRDY3/AN11
P94/RTP1/AN12
P95/RTP0/AN13
P96/PWM0/AN14
P97/BUZ02/AN15
A-D conversion register (L)
VREF
A-D CONVERTER
The 38B7 group has a 10-bit A-D converter. The A-D converter
performs successive approximation conversion.
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the A-D conversion register (high-order) (address
003416), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the A-D conversion register (low-order) (address
003316).
During A-D conversion, do not read these registers.
[AD/DA Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input
pin selection bits. Bit 4 is an AD conversion completion bit and “0”
during A-D conversion. This bit is set to “1” upon completion of A-
D conversion.
A-D conversion is started by writing “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVss and VREF by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA7/AN7–PA0/
AN0, and P97/BUZ02/AN15 to P90/SIN3/AN8 and inputs it to the
comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog
inputvoltage with the comparison voltage and stores the result in
the A-D conversion register. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
that set f(XIN) to at least 250 kHz during A-D conversion. Addition-
ally, bit 7 of the CPU mode register (address 003B16) must be set
to “0”.
Fig. 61 Block diagram of A-D converter
Fig. 60 Structure of AD/DA control register
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