參數(shù)資料
型號(hào)： M38B79MFH-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 77/112頁
文件大?。?/td> 1862K
代理商： M38B79MFH-XXXXFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
64
P96/PWM0 output selection bit
0: I/O port
1: PWM0 output
Not used (return “0” when read)
PWM control register
(PWMCON: address 002616)
b7
b0
6A
6B
6A
6B
5
6A
6B
6A
6B
6A
6B
6A
4
3
4
3
4
3
4
6B
6A
69
68
67
02
01
6A
69
68
67
02
01
02
01
00
FF
FE
FD
97
96
95
02
01
00
FC
FF
FE
FD
97
96
95
FC
ADD
165316
1A9316
1AA416
1EE416
1EF516
T = 4096
s
t = 64
s
1316
A416
2416
3516
7B16
6A16
5916
Data 3516 stored at address 003616
t = 64
s
τ = 0.25 s
“H” period length specified by PWMH
1
2
B516
2
PWM register
(high-order)
PWM register
(low-order)
PWM latch
(14-bit)
Data 6A16 stored at address 003516
Data 2416 stored at address 003616
Bit 7 cleared after transfer
Transfer from register to latch
Data 7B16 stored at address 003516
Transfer from register to latch
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
PWM output
(Example 1)
Low-order 6-bits
output
H = 6A16
L = 2416
6B16............36 times
(107)
6A16............28 times
(106)
PWM output
(Example 2)
Low-order 6 bits
output
H = 6A16
L = 1816
6B16............24 times
6A16............40 times
PWM output
8-bit counter
The ADD portions with
additional
τ are determined
either “H” or “L” by low-order
6-bit data.
Minimum bit width
(64 64
s)
106 64 + 24
(256 0.25
s)
256
τ (64 s), fixed
106 64 + 36
Fig. 67 14-bit PWM timing
Fig. 66 Structure of PWM control register
相關(guān)PDF資料
PDF描述
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