參數(shù)資料
型號(hào)： M38B79MFH-XXXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 45/112頁(yè)
文件大?。?/td> 1862K
代理商： M38B79MFH-XXXXFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
35
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which in-
forms the serial transfer destination that transmit/receive is ready.
In the initial status, when the serial I/O initialization bit (b4) is reset
to “0”, the SRDY1 output goes to “L” and the SRDY1 output goes to
“H”. After transmitted data is stored in the serial I/O1 register (ad-
dress 001B16) and a transmit/receive operation becomes ready,
the SRDY1 output goes to “H” and the SRDY1 output goes to “L”.
When a transmit/receive operation is started and the transfer clock
goes to “L”, the SRDY1 output goes to “L” and the SRDY1 output
goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the se-
rial transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles
or more of transfer clock, transfer clocks are output from the
SCLK1 output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received,
the transfer clocks from the SCLK1 output is stopped. The hand-
shake unit of the 8-bit serial I/O and that of the automatic transfer
serial I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (SBUSY1 output: “L”, SBUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an
“L” level signal into the SRDY1 input, and also write transmit data
into the serial I/O1 register.
Fig. 32 SRDY1 output operation
Fig. 33 SRDY1 input operation (internal synchronous clock)
SRDY1
SCLK1
Write to serial
I/O1 register
SRDY1
SCLK1
SOUT1
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