參數(shù)資料
型號(hào)： M38B79MFH-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 56/112頁(yè)
文件大?。?/td> 1862K
代理商： M38B79MFH-XXXXFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
45
Fig. 45 Structure of FLDC related registers (1)
b7 b6 b5
b4 b3
b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display (start to display by switching “0” to “1”)
Tscan control bits
b3b2
0 0 : FLD digit interrupt (at rising edge of each digit)
0 1 : 1 Tdisp
1 0 : 2 Tdisp
FLD blanking interrupt
1 1 : 3 Tdisp
(at falling edge of the last digit)
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16
1 : f(XIN)/64
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Note: When the gradation display mode is selected, the max. number of timing is 16
timing. (Be sure to set the timing number control bit to “0”.)
b7 b6 b5
b4 b3
b2 b1 b0
FLD output control register
(FLDCON: address 0EFC16)
P64 to P67 output reverse bit
0 : Output normally
1 : Reverse output
Not used (return “0” when read); (Do not write “1”.)
P64 to P67 Toff invalid bit
0 : Operation normally
1 : Toff invalid
Not used (return “0” when read); (Do not write “1”.)
P73 dimmer output control bit
0 : Normal port
1 : Dimmer output
Generating/Not of CMOS port Toff section selection bit
0 : Toff section not generated
1 : Toff section generated
Generating/Not of high-breakdown voltage port Toff section
selection bit
0 : Toff section not generated
1 : Toff section generated
Toff2 SET/RESET switch bit
0 : Toff2 RESET; Toff1 SET
1 : Toff2 SET; Tdisp RESET
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