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參數(shù)資料
| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 52/112頁 |
| 文件大?。?/td> | 1862K |
| 代理商： | M38B79MFH-XXXXFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
41
Serial I/O3
The serial I/O3 function can be used only for 8-bit clock synchro-
nous serial I/O.
All serial I/O pins are shared with port P9, which can be set with
the serial I/O3 control register (address 0EEC16).
[Serial I/O3 Control Register (SIO3CON)] 0EEC16
The serial I/O3 control register contains eight bits which control
various serial I/O functions.
q Serial I/O3 Operation
Either the internal clock or external clock can be selected as syn-
chronous clock for serial I/O3 transfer.
The internal clock can use a built-in dedicated divider where 6 dif-
ferent clocks are selected. In the case of the internal clock used,
transfer is started by a write signal to the serial I/O3 register (ad-
dress 0EED16). When 8-bit data has been transferred, the SOUT3
pin goes to high impedance state.
In the case of the external clock used, the clock must be externally
controlled. It is because the contents of serial I/O3 register is kept
shifted while the clock is being input. Additionally, the function to
put the SOUT3 pin high impedance state at completion of data
transfer is not available.
The serial I/O3 interrupt request bit is set at completion of 8-bit
data transfer, regardless of use of the internal clock or external
clock.
Fig. 42 Structure of serial I/O3 control register
Fig. 41 Block diagram of serial I/O3
“1”
“0”
“1”
“0”
“1”
SRDY3
S
C
L
K
3
“0”
“1”
1/4
1/8
1/16
1/32
1/64
1/128
Data bus
Serial I/O3
interrupt request
Serial I/O3 port selection bit
Serial I/O3 counter (3)
Serial I/O3 shift register (8)
Synchronization
circuit
Serial I/O3 port selection bit
Serial I/O3 synchronous
clock selection bit
SRDY3 output selection bit
External clock
Internal synchronous
clock selection bits
D
iv
id
e
r
P92/SCLK3
P91/SOUT3
P90/SIN3
P92 latch
P91 latch
P93 latch
P93/SRDY3
XCIN
1/2
XIN
“0”
“1”
Internal system clock
selection bit
Serial I/O3 control register
(SIO3CON : address 0EEC16)
b7
Internal synchronous clock selection bits
0 0 0: f(XIN)/4 (f(XCIN)/8)
0 0 1: f(XIN)/8 (f(XCIN)/16)
0 1 0: f(XIN)/16 (f(XCIN)/32)
0 1 1: f(XIN)/32 (f(XCIN)/64)
1 1 0: f(XIN)/64 (f(XCIN)/128)
1 1 1: f(XIN)/128 (f(XCIN)/256)
Serial I/O3 port selection bit (P91, P92)
0: I/O port
1: SOUT3, SCLK3 signal output
SRDY3 output selection bit (P93)
0: I/O port
1: SRDY3 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O3 synchronous clock selection bit
0: External clock
1: Internal clock
P9/SOUT3 P-channel output disable bit (P91)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
b0
b2 b1 b0
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