
LOW VOLTAGE VERSION
7702/7703 Group User’s Manual
18–35
18.6 Application
Some application examples of connecting external memorys for the low voltage version are described
bellow.
Applications shown here are just examples. Modify the desired application to suit the user’s need and make
sufficient evaluation before actually using it.
18.6.1 Memory expansion
The following items of the low voltage version are the same as those of section “17.1 Memory expansion.”
However, a part of the formulas and constants for parameters is different.
Memory expansion model
Formulas for address access time of external memory
Bus timing
Memory expansion method
Address access time of external memory ta(AD)
ta(AD) = td(P0A/P1A/P2A–E) + tw(EL) – tsu(P2D/P1D-E) – (address decode time
V1 + address latch delay
time
V2)
td(P0A/P1A/P2A–E) : td(P0A–E), td(P1A–E), or td(P2A–E)
tsu(P2D/P1D–E) : tsu(P2D–E), or tsu(P1D–E)
address decode timeV1 : time necessary for validating a chip select signal after an address is decoded
address latch delay time
V2
: delay time necessary for latching an address
(This is not necessary on the minimum model.)
Data setup time of external memory for writing data tsu(D)
tsu(D) = tw(EL) – td(E–P2Q/P1Q)
td(E–P2Q/P1Q) : td(E–P2Q), or td(E–P1Q)
Table 18.6.1 lists the calculation formulas and constants for each parameter of the low voltage version.
Figure 18.6.1 shows the relationship between ta(AD) and f(XIN). Figure 18.6.2 shows the relationship between
tsu(D) and f(XIN).
Table 18.6.1 Calculation formulas and constants
for each parameter (Unit : ns)
Parameter
td(P0A-E)
td(P1A-E)
td(P2A-E)
tw(EL)
tsu(P1D-E)
tsu(P2D-E)
td(E-P1Q)
td(E-P2Q)
tpxz(E-P1Z)
tpxz(E-P2Z)
tpzx(E-P1Z)
tpzx(E-P2Z)
No wait
Wait
f(XIN)
≤ 8 MHz
f(XIN)
1 ! 109
f(XIN)
50 +
– 125
2 ! 109
f(XIN)
– 40
4 ! 109
f(XIN)
– 40
80
130
10
1 ! 109
f(XIN)
– 30
Note: For M37702E2LXXXGP and M37702E4LXXXFP,
refer to section “19.5.4 Bus timing and EPROM
mode.”
(Note)