
7702/7703 Group User’s Manual
7–47
SERIAL I/O
7.4 Clock asynchronous serial I/O (UART) mode
Fig. 7.4.8 Initial setting example for relevant registers when receiving
Reception starts when the start
bit is detected.
Port P8 direction register (Address 1416)
b7
b0
0
RxD0 pin
RxD1 pin
UART0 baud rate register (BRG0) (Address 3116)
UART1 baud rate register (BRG1) (Address 3916)
b7
b0
Set to 00
to FF .
UART0 receive interrupt control register (Address 7216)
UART1 receive interrupt control register (Address 7416)
b7
b0
Interrupt priority level select bits
When using interrupts, set these bits to
level 1–7.
When disabling interrupts, set these bits
to level 0.
Note: Set the transfer data format in
the same way as set on the
transmitter side.
1
UART0 transmit/receive control register 1 (Address 3516)
UART1 transmit/receive control register 1 (Address 3D16)
b7
b0
Receive enable bit
1: Reception enabled
UART0 transmit/receive mode register (Address 30
)
UART1 transmit/receive mode register (Address 38
)
b7
b0
Internal/External clock select bit
0: Internal clock
1: External clock
1 0 0: UART mode (7 bits)
1 0 1: UART mode (8 bits)
1 1 0: UART mode (9 bits)
Stop bit length select bit
0: 1 stop bit
1: 2 stop bits
Odd/Even parity select bit
0: Odd parity
1: Even parity
Parity enable bit
0: Parity disabled
1: Parity enabled
Sleep select bit
0: Sleep mode cleared (ignored)
1: Sleep mode selected
1
b2b1b0
UART0 transmit/receive control register 0 (Address 34
)
UART1 transmit/receive control register 0 (Address 3C )
b7
b0
BRG count source select bits
CTS
/RTS select bit
0 : CTS function selected
1 : RTS function selected
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
b1b0
16