
CONNECTION WITH EXTERNAL DEVICES
7702/7703 Group User’s Manual
12–7
12.1 Signals required for accessing external devices
(9)
Clock
φ1
This signal has the same period as
φ.
In the memory expansion mode, this signal is output externally by setting the clock
φ1 output select
bit (bit 7 at address 5E16) to “1.” Figure 12.1.3 shows the output start timing of clock
φ1.
In the microprocessor mode, this signal is always output externally.
Note: Even in the single-chip mode, the clock
φ1 can be output externally. This signal is output
externally by setting the clock
φ1 output select bit to “1” just as in the memory expansion
mode.
Fig. 12.1.3 Output start timing of clock
φ1
Writing “1” to clock
1
output select bit
E
Clock
1
(P42)
Notes 1: The 1st cycle of clock
1
may be shortened; indicated by
.
2: This applies when writing to clock
1
output select bit while
P42 pin is outputting “L” level.
Bit
Bit name
Functions
At reset
RW
0
1
2
3
4
5
6
7
Processor mode bits
Software reset bit
Interrupt priority detection time
select bits
Clock
1
output select bit
(Note 2)
0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not selected
The microcomputer is reset by
writing “1” to this bit. The value is
“0” at reading.
0 0 : 7 cycles of
0 1 : 4 cycles of
1 0 : 2 cycles of
1 1 : Not selected
0 : Clock
1
output disabled
(P42 functions as a programmable
I/O port.)
1 : Clock
1
output enabled
(P42 functions as a clock
1
out-
put pin.)
0
b1 b0
b5 b4
Processor mode register (Address 5E16)
(Note 1)
Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1”
after a reset. (Fixed to “1.”)
2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)
b1
b0
b2
b3
b4
b5
b6
b7
0
RW
Wait bit
RW
WO
0
RW
0
RW
Fix this bit to “0.”
RW
0 : Software Wait is inserted when
accessing external area.
1 : No software Wait is inserted
when accessing external area.
: Bits 0 to 6 are not used for setting of clock
1
output.
Fig. 12.1.4 Structure of processor mode register