
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
68
Wipe speed
The wipe speed is determined by the vertical synchronization (V
SYNC
)
signal. For the NTSC interlace method, assuming that
V
SYNC
= 16.7 ms, 262.5 H
SYNC
signals (per field)
we obtain the wipe speed as shown in Table 14.
Wipe resolution varies with each wipe mode. In mode 1 and mode 2,
one of 3 resolutions (1H, 2H, 4H) can be selected. In mode 3, wipe is
done in units of 4H only.
Table 14. Wipe Speed
(NTSC interlace method, H = 262.5)
Wipe Speed (entire screen)
16.7 (ms)
262.5
÷
1
16.7 (ms)
262.5
÷
2
16.7 (ms)
262.5
÷
4
4 (s)
2 (s)
1 (s)
Table 15. Wipe Mode and Wipe Resolution
Wipe Resolution
Mode
Wipe Resolution
1H Unit
2H Unit
4H Unit
1H Unit
2H Unit
4H Unit
4H Unit
Wipe Speed
about 4 (s)
about 2 (s)
about 1 (s)
about 1 (s)
Mode 1
Mode 2
Mode 3
Fig. 63. Structure of Wipe Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Wipe mode register (SL) [Address 00ED
16
]
B
Name
Functions
After reset
R W
Wipe Mode Register
0, 1 Wipe mode selection bits
(SL0, SL1)
b1 b0
0 0 : Wipe is not available
0 1 : Mode 1
1 0 : Mode 2
1 1 : Mode 3
0
2
Direction mode selection
bits (SL2)
0
R W
R W
7
0
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is indeterminate.
R —
3, 4 Wipe unit selection bits
(SL3, SL4)
0
R W
0: DOWN mode
1: UP mode
b4 b3
0 0 : 1H unit
0 1 : 2H unit
1 0 : 3H unit
1 1 : Do not set
5, 6 Stop mode selection bits
(SL5, SL6)
0
R W
b6 b5
0 0 : Stop at the 312nd H
0 1 : Stop at the 156th H
1 0 : Stop at the 256th H
1 1 : Stop at the 128th H