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參數(shù)資料
| 型號(hào)： | M3720-1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1 KEY 1 SOUND |
| 中文描述： | 1鍵1聲 |
| 文件頁數(shù)： | 36/121頁 |
| 文件大小： | 1907K |
| 代理商： | M3720-1 |
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36
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
(9) START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 33 and Table 4. Only when the 3 conditions of Table 4 are
satisfied, a START/STOP condition can be detected.
Note:
When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated
to the CPU.
(8) STOP Condition Generation Method
When the ES0 bit of the I
2
C control register (address 00DC
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00DB
16
)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 32 for
the STOP condition generation timing diagram, and Table 3 for the
START condition/STOP condition generation timing table.
Fig. 32. STOP Condition Generation Timing Diagram
Fig. 33. START Condition/STOP Condition Detect Timing
Diagram
Table 4. START Condition/STOP Condition Detect Conditions
Table 3. START Condition/STOP Condition Generation Timing
Table
Item
Setup time
Hold time
Set/reset time
for BB flag
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
Standard Clock Mode
5.0 μs (20 cycles)
5.0 μs (20 cycles)
3.0 μs (12 cycles)
High-speed Clock Mode
2.5 μs (10 cycles)
2.5 μs (10 cycles)
1.5 μs (6 cycles)
I
2
C status register
write signal
Reset time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Hold time
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Hold time
Setup
time
(6) START Condition Generation Method
When the ESO bit of the I
2
C control register (address 00DC
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00DB
16
)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “000
2
” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 31 for the START condition gen-
eration timing diagram, and Table 3 for the START condition/STOP
condition generation timing table.
Fig. 31. START Condition Generation Timing Diagram
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence:
Set “20
16
” to the I
2
C status register (S1).
Write a transmit data to the I
2
C data shift register.
Set “F0
16
” to the I
2
C status register (S1) again.
<Example of Setting of RESTART Condition>
I
2
C status register
; S1 = 20
16
I
2
C data shift register ; S0 = transmit data after restart
I
2
C status register
; S1 = F0
16
I
2
C status register
write signal
Set time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Setup
time
Standard Clock Mode
6.5 μs (26 cycles) <
SCL
release time
3.25 μs (13 cycles) < Setup time
3.25 μs (13 cycles) < Hold time
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses de-
notes the number of
φ
cycles.
High-speed Clock Mode
1.0 μs (4 cycles) <
SCL
release time
0.5 μs (2 cycles) < Setup time
0.5 μs (2 cycles) < Hold time
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M3720-10 | 1 KEY 1 SOUND |
| M3720-2 | 1 KEY 1 SOUND |
| M3720-3 | 1 KEY 1 SOUND |
| M3720-4 | 1 KEY 1 SOUND |
| M3720-5 | 26604060VOID34 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3720-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
| M3720-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1 KEY 1 SOUND |
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