
MITSUBISHI MICROCOMPUTERS
M37207MF-XXXSP/FP, M37207M8-XXXSP
M37207EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
and ON-SCREEN DISPLAY CONTROLLER
19
Fig. 10. Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC
B
0
Name
Functions
After reset
R W
0
Interrupt Request Register 1
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit (TM1R)
Timer 2 interrupt
request bit (TM2R)
Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
request bit (TM4R)
CRT interrupt
request bit (CRTR)
V
SYNC
interrupt
request bit (VSCR)
Multi-master I
2
C-BUS
interface interrupt
request bit (IICR)
1
2
3
4
5
6
0
0
8
0
8
0
8
0
8
0
8
8
8
16
]
R
R
R
R
R
R
R
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
—
R
0
Fig. 11. Interrupt Request Register 2
b7b6 b5b4b3 b2b1b0
0
Interrupt request register 2 (IREQ2) [Address 00FD
B
0
Name
Functions
After reset
R W
Interrupt Request Register 2
INT1 interrupt
request bit (ITIR)
INT2 interrupt
request bit (IT2R)
Serial I/O interrupt
request bit (SIR)
3,6
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
1
2
4
f(X
IN
)/4096 interrupt
request bit (MSR)
Timer 5 6 interrupt
request bit (TM56R)
7
Fix this bit to “0.”
0
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
8
: “0” can be set by software, but “1” cannot be set.
0
8
0
0
8
0
8
0
8
16
]
R
R
R
R —
R
R W
5
0
8
R