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參數(shù)資料
| 型號： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
6 of 12
Revised 29Apr2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
Narrow Bandwidth (NBW) Pin
The M2006-04 includes a manual narrow bandwidth
(NBW) setting that can be selectively enabled by
asserting the NBW input (pin 32) to logic 1. When the NBW
pin is logic 0, the M2006-04 operates in the nominal
wider bandwidth mode.
If either NBW pin or the serially programmed T2 bit is
asserted (logic 1, HIGH), the device goes into
Narrow Bandwidth mode. See Table 4, Serial
In relation to the APS circuit, the NBW setting functions
as follows:
Setting NBW to logic 1, the NBW function overrides the
APS circuit to force narrow bandwidth mode.
Setting NBW to logic 0, the APS circuit can
automatically turn on and off narrow bandwidth
mode.
The NBW pin operates by controlling the values of R
IN,
an internal loop filter component as illustrated in Figure
R
IN = 16k. When NBW is asserted to logic 1, RIN is
increased to 2M
.
Compared to normal operation (when pin NBW = logic 0),
setting NBW to logic 1 does the following:
Loop bandwidth is decrease by a factor of 40
Loop damping factor is decreased by a factor of 6.3
Indiscriminate use of the NBW pin can lead to an
under damped loop configuration. A loop damping
factor of >0.5 should be maintained to assure stable
loop operation.
The NBW pin is useful for two main applications:
NBW can be selectively asserted high to manually
assert and hold a temporary narrow loop bandwidth
operation during the phase locking to a newly
selected clock reference input. When configured with
the right loop filter component values, this can assure
that M2006-04 clock output slew rate is sufficiently
decreased to meet GR-253-CORE MTIE and TDEV.
NBW can be tied to logic 1 to permanently enable
lower loop bandwidth which might be preferred for a
given jitter attenuation application.
Loop Bandwidth Calculator
A free loop bandwidth calculator is available.
Call 508-852-5400, ICS Communications Modules
business unit (CMBU), Worcester, MA.
This calculator can be used to determine the loop filter
values needed to obtain a desired loop bandwidth and
damping factor. Pass band peaking can also be
calculated. The calculator is also useful for
understanding the effect of the NBW selection on loop
filter characteristics.
NBW Pin
Setting
(Pin 32)
Internal
Value R
IN
1
Note 1: With the same set of loop filter components
PLL Configuration
(Loop Bandwidth)
0
50k
Normal Loop Bandwidth
1
2M
Narrow Loop Bandwidth
Table 7: NBW Pin Settings
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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