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參數(shù)資料
| 型號(hào)： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
4 of 12
Revised 29Apr2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
FUNCTIONAL DESCRIPTION
The M2006-04 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of three selectable input reference clocks.
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
The M2006-04 will default to a multiplying factor of 32
on power-up. The multiplying factor can be changed by
serially programming the input and feedback dividers by
way of the serial programming register.
A differential LVPECL signal provides the output clock
for the device. A second differential output, which can
be programmed to divide the output frequency by a
factor of 4, is also available. The output frequency can
be momentarily increased or decreased to add or
subtract one net output clock cycle by asserting the
ADD_CLK
or DROP_CLK inputs, respectively.
An external loop filter sets the PLL bandwidth which can
be optimized to provide jitter attenuation of the input
reference clock.
The frequency agility, bandwidth control, and protection
switch features make the M2006-04 ideal for use as a
clock jitter attenuator, frequency translator, and clock
frequency generator in OC-3 through OC-192
applications.
Input Reference Clocks
One input reference clock is selected from among two
differential LVPECL clocks and one single-ended
LVCMOS / LVTTL clock. The maximum input frequency
is 700MHz.
The input reference clock is selected from DIF_CLK 0,
DIF_CLK 1
, or REF_CLK by selecting the appropriate
REF_SEL0
and REF_SEL1 inputs.
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The “M Divider” divides the VCSO frequency, feeding
the result into the phase detector. The selected input
reference clock is divided by the “R Divider”. The result
is fed into the other input of the phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
M Divider, R Divider, and VCSO Frequency
The relationship between the VCSO (Fvcso) frequency,
the M and R dividers, and the input reference frequency
(Fref_clk) is:
The ratio of M/R times input frequency must be such
that it falls within the "lock" range of the VCSO.
On power-up the M and R dividers are set to 32 and 1,
respectively. The M divider (10-bits) can be programmed
for a maximum value of 1023 and a minimum value of 4.
The R divider (9-bits) can be set to a maximum value of
511 and a minimum value of 1.
P Divider and Outputs
The M2006-04 provides a total of two differential
LVPECL output pairs: FOUT0 and FOUT1. FOUT0 operates
at the VCSO frequency while FOUT1 can operate at the
VCSO frequency (Fvcso) or 1/4 Fvcso.
For example, FOUT1 can output 155.52MHz while
FOUT0 outputs 622.08MHz.
One output divider (the “P” divider) is for the FOUT1
output pair. The P divider divides the VCSO frequency
to produce one of two output frequencies (Fvcso or
1/4 Fvcso). The P1 pin selects the value for the P
divider: logic 1 sets P to 4, logic 0 sets P to 1.
Fvcso
Fref_clk
M
R
--------
×
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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