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參數(shù)資料
| 型號(hào)： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
3 of 12
Revised 29Apr2003
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
Reference Clock Input Selection
Serial Programming M and R Divider Values *
P Divider Selection
M2006-04
VC
nVC
nOP_OUT
OP_OUT
OP_IN
nOP_IN
M = 3-1023
Power-Up Default = 32
Serial
Configuration
Register
nFOUT0
S_DATA
S_CLOCK
S_LOAD
R = 1-511
Power-Up
Default = 1
MUX
00
01
1
x
NBW
R8:0
M9:0
T2
REF_SEL1:0
Pin Settings
(Pins 22, 29)
Reference Input Selection
0
DIF_REF0, nDIF_REF0
0
1
DIF_REF1, nDIF_REF1
1
0
REF_CLK
1
Table 3: Reference Clock Input Selection
Serial
Bits
Settings per Bit
Definition
T2:0
2 1 0
Bandwidth and Test Values
0 0 0
Normal Bandwidth
*
1 0 0
Narrow Bandwidth
*
Note: T1 and T0, used for test automation, must be set to 0
R8:0
8 7 6 5 4 3 2 1 0
Feedback Divider Value “R”
0 0 0 0 0 0 0 0 1
R = 1 minimum, power-up default
0 0 0 1 0 0 0 0
R = 16
1 1 1 1 1 1 1 1
R = 511
maximum
M9:0 9 8 7 6 5 4 3 2 1 0
Reference Divider Value “M”
0 0 0 0 0 0 0 0 1 1
M = 3
minimum
0 0 0 0 1 0 0 0 0 0
M = 32
power-up default
1 1 1 1 1 1 1 1 1 1
M = 1023
maximum
Note *: If either the T2 bit or the NBW pin is asserted (logic 1,
HIGH), the device goes into Narrow Bandwidth mode.
See also Figure 4, Serial Configuration Register, on
pg. 5 and the subsection titled Narrow Bandwidth (NBW)
P1 Pin Setting
(Pin 17)
P Divider
Value
M2006-04-622.0800
Output Frequency,
FOUT1
(MHz)
1
4
155.52
0
1
622.08
Table 5: P Divider Selector, Values, and Frequencies
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相關(guān)代理商/技術(shù)參數(shù) |
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| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
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| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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